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參數(shù)資料
| 型號(hào)： | GS8662D11BGD-400 |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | SRAM |
| 英文描述： | 8M X 9 STANDARD SRAM, 0.45 ns, PBGA165 |
| 封裝： | 13 X 15 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165 |
| 文件頁數(shù)： | 2/34頁 |
| 文件大?。?/td> | 670K |
| 代理商： | GS8662D11BGD-400 |
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Separate I/O SigmaQuad II+ B4 SRAM Truth Table
Previous
Operation
A
R
W
Current
Operation
D
Q
K
↑
(tn-1)
K
↑
(tn)
K
↑
(tn)
K
↑
(tn)
K
↑
(tn)
K
↑
(tn+1)
K
↑
(tn+1)
K
↑
(tn+2)
K
↑
(tn+2)
K
↑
(tn+2)
K
↑
(tn+3)
K
↑
(tn+3)
K
↑
(tn+4)
Deselect
X
1
Deselect
X
—
Hi-Z
—
Write
X
1
X
Deselect
D2
D3
—
Hi-Z
—
Read
X
1
Deselect
X
—
Q2
Q3
—
Deselect
V
1
0
Write
D0
D1
D2
D3
Hi-Z
—
Deselect
V
0
X
Read
X
—
Q0
Q1
Q2
Q3
Read
V
X
0
Write
D0
D1
D2
D3
Q2
Q3
—
Write
V
0
X
Read
D2
D3
—
Q0
Q1
Q2
Q3
Notes:
1. “1” = input “high”; “0” = input “l(fā)ow”; “V” = input “valid”; “X” = input “don’t care”
2. “—” indicates that the input requirement or output state is determined by the next operation.
3. Q0, Q1, Q2, and Q3 indicate the first, second, third, and fourth pieces of output data transferred during Read operations.
4. D0, D1, D2, and D3 indicate the first, second, third, and fourth pieces of input data transferred during Write operations.
5. Users should not clock in metastable addresses.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.02 3/2011
10/34
2011, GSI Technology
GS8662D20/38BD-550/500/450/400/350
GS8662D06/11BD-500/450/400/350
Byte Write Clock Truth Table
BW
Current Operation
D
K
↑
(tn+1)
K
↑
(tn+1)
K
↑
(tn+2)
K
↑
(tn+2)
K
↑
(tn)
K
↑
(tn+1)
K
↑
(tn+1)
K
↑
(tn+2)
K
↑
(tn+2)
T
Write
Dx stored if BWn = 0 in all four data transfers
D0
D2
D3
D4
T
F
Write
Dx stored if BWn = 0 in 1st data transfer only
D0
X
F
T
F
Write
Dx stored if BWn = 0 in 2nd data transfer only
X
D1
X
F
T
F
Write
Dx stored if BWn = 0 in 3rd data transfer only
X
D2
X
F
T
Write
Dx stored if BWn = 0 in 4th data transfer only
X
D3
F
Write Abort
No Dx stored in any of the four data transfers
X
Notes:
1. “1” = input “high”; “0” = input “l(fā)ow”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.
2. If one or more BWn = 0, then BW = “T”, else BW = “F”.
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PDF描述 |
|---|---|
| GS8662D36BD-300IT | 2M X 36 STANDARD SRAM, 0.45 ns, PBGA165 |
| GS8662DT10BGD-400IT | 8M X 9 QDR SRAM, 0.45 ns, PBGA165 |
| GS8662Q18BD-357 | 4M X 18 STANDARD SRAM, 0.45 ns, PBGA165 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS8662D18BGD-300I | 制造商:GSI Technology 功能描述:GS8662D18BGD-300I - Trays |
| GS8662D18E-167 | 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb SigmaQuad-II Burst of 4 SRAM |
| GS8662D18E-167I | 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb SigmaQuad-II Burst of 4 SRAM |
| GS8662D18E-200 | 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb SigmaQuad-II Burst of 4 SRAM |
| GS8662D18E-200I | 制造商:GSI 制造商全稱:GSI Technology 功能描述:72Mb SigmaQuad-II Burst of 4 SRAM |
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