參數(shù)資料
型號: GS8180S09
廠商: GSI TECHNOLOGY
英文描述: 2Mb x 9Bit Separate I/O Sigma DDR SRAM(2M x 9位獨立I/O接口雙數(shù)據(jù)速率讀和寫模式靜態(tài)ΣRAM)
中文描述: 2MB的x 9Bit分離I / O西格瑪?shù)腄DR SRAM的(2米× 9位獨立的I / O接口雙數(shù)據(jù)速率讀和寫模式靜態(tài)ΣRAM)
文件頁數(shù): 3/32頁
文件大小: 853K
代理商: GS8180S09
Rev: 1.01 11/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
3/32
2000, Giga Semiconductor, Inc.
A
Advanced Information
GS8180S09/18/36B-333/300/275/250
8180
S
18 Pinout
1M x 18 Separate I/O—Top View
1
2
3
4
5
6
7
8
9
10
11
A
Db1
Db2
A
E2
A
(16M)
MCL
A
(8M)
E3
A
NC
NC
B
Db3
Db4
MCL
NC
A
W
A
NC
NC
NC
NC
C
Db5
Db6
NC
NC
NC
(128M)
E1
A
NC
MCL
NC
NC
D
Db7
Db8
V
SS
NC
NC
MCL
NC
NC
V
SS
NC
NC
E
Db9
Qb1
V
DDQ
V
DDQ
V
DD
V
DD
V
DD
V
DDQ
V
DDQ
NC
NC
F
Qb3
Qb2
V
SS
V
SS
V
SS
ZQ
V
SS
V
SS
V
SS
NC
NC
G
Qb5
Qb4
V
DDQ
V
DDQ
V
DD
EP2
V
DD
V
DDQ
V
DDQ
NC
NC
H
Qb7
Qb6
V
SS
V
SS
V
SS
EP3
V
SS
V
SS
V
SS
NC
NC
J
Qb9
Qb8
V
DDQ
V
DDQ
V
DD
M4
V
DD
V
DDQ
V
DDQ
NC
NC
K
CQ2
CQ2
CK
NC
V
SS
MCL
V
SS
NC
NC
CQ1
CQ1
L
NC
NC
V
DDQ
V
DDQ
V
DD
M2
V
DD
V
DDQ
V
DDQ
Qa8
Qa9
M
NC
NC
V
SS
V
SS
V
SS
M3
V
SS
V
SS
V
SS
Qa6
Qa7
N
NC
NC
V
DDQ
V
DDQ
V
DD
MCH
V
DD
V
DDQ
V
DDQ
Qa4
Qa5
P
NC
NC
V
SS
V
SS
V
SS
MCL
V
SS
V
SS
V
SS
Qa2
Qa3
R
NC
NC
V
DDQ
V
DDQ
V
DD
V
DD
V
DD
V
DDQ
V
DDQ
Qa1
Da9
T
NC
NC
V
SS
NC
NC
MCL
NC
NC
V
SS
Da8
Da7
U
NC
NC
NC
A
NC
(64M)
A
NC
(32M)
A
NC
Da6
Da5
V
NC
NC
A
(2M)
A
A
A1
A
A
A
(4M)
Da4
Da3
W
NC
NC
TMS
TDI
A
MCL
A
TDO
TCK
Da2
Da1
Rev 10
11 x 19 Bump BGA—14 x 22 mm2 Body—1 mm Bump Pitch—MS-028vBC
Note:
Users of CMOS I/O Sigma RAMs may wish to connect D4, D8, T4, T8 and K4 to V
DDQ
/2 to allow alternate use of HSTL
I/O Sigma RAMs.
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