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參數(shù)資料
| 型號： | GS8180S09 |
| 廠商： | GSI TECHNOLOGY |
| 英文描述： | 2Mb x 9Bit Separate I/O Sigma DDR SRAM(2M x 9位獨(dú)立I/O接口雙數(shù)據(jù)速率讀和寫模式靜態(tài)ΣRAM) |
| 中文描述： | 2MB的x 9Bit分離I / O西格瑪?shù)腄DR SRAM的（2米× 9位獨(dú)立的I / O接口雙數(shù)據(jù)速率讀和寫模式靜態(tài)ΣRAM） |
| 文件頁數(shù)： | 13/32頁 |
| 文件大?。?/td> | 853K |
| 代理商： | GS8180S09 |
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Rev: 1.01 11/2000
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
13/32
2000, Giga Semiconductor, Inc.
A
Advanced Information
GS8180S09/18/36B-333/300/275/250
.Separate I/O Sigma RAM Bank Switch with E1 Deselect
FLXDrive Output Driver Impedance Control
The ZQ pin allows selection between
Σ
RAM nominal drive strength (ZQ low) for multi-drop bus applications and low drive
strength (ZQ floating or high) point-to-point applications. See the Output Driver Characteristics chart for details.
DF0
DF1
DC0
DC1
Note:
1 E1\ does not deselect the Echo Clock Outputs. Echo Clock outputs are synchronously deselected by E2 or E3 being sampled false.
2 Reads or Writes launched in a bank continue in the same bank.
QE1
H
I
Write
Bank 1
QG0
QG0
QE1
QE0
CQ
Bank 1
CQ
Bank 2
CQ1 + CQ2
Q Bank 1 +
Q Bank 2
QB0
QB1
Q
Bank 2
QB0
QB1
D
Bank 2
/E2 Bank 1
E2 Bank 2
Q
Bank 1
QE0
G
/E
1
/W
D
Bank 1
C
D
E
F
CK
Address
XX
B
Read
Bank 1
Write
Bank 1
Read
Bank 1
-
Bank 2
Bank 2
Both
No Op
Read
Write
Deselect
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| GS8182D08BD-167 | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V 16MBIT 2MX8 0.5NS 165FPBGA - Trays |
| GS8182D08BD-250 | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V 16MBIT 2MX8 0.45NS 165FPBGA - Trays |
| GS8182D08BD-375 | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V 16MBIT 2MX8 0.45NS 165FPBGA - Trays |
| GS8182D09BD-400 | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V 18MBIT 2M X 9 0.45NS 165FPBGA - Trays |
| GS8182D18BD-167 | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V 18MBIT 1MX18 0.5NS 165FPBGA - Trays |
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