參數(shù)資料
型號: GS8170DW72AC-250IT
廠商: GSI TECHNOLOGY
元件分類: SRAM
英文描述: 256K X 72 STANDARD SRAM, 2.1 ns, PBGA209
封裝: 14 X 22 MM, 1 MM PITCH, BGA-209
文件頁數(shù): 6/32頁
文件大?。?/td> 1038K
代理商: GS8170DW72AC-250IT
GS8170DW36/72AC-350/333/300/250
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04 4/2005
14/32
2003, GSI Technology
Common I/O State Diagram
Notes:
1. The notation “X,X,X,X” controlling the state transitions above indicate the states of inputs E1, E, ADV, and W respectively.
2. If (E2 = EP2 and E3 = EP3) then E = “T” else E = “F”.
3. “1” = input “high”; “0” = input “l(fā)ow”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.
Deselect
Bank
Deselect
Read
Write
Continue
X,F,0,X or X,X,1,X
Continue
X,F,0,X
1,T,0,X
X,F,0,X
1,T,0,X
X,F,0,X
1,T,0,X
1,T,0,X or X,X,1,X
0,T,0,0
0,T,0,1
0,T,0,0
0,T,0,1
X,F,0,X
0,T,0,0
0,T,0,1
X,X,1,X
0,T,0,0
0,T,0,1
1,T,0,X
0,T,0,0
0,T,0,1
X,X,1,X
0,T,0,1
0,T,0,0
Clock (CK)
Command
Current State
Next State
Current State & Next State Definition for Read
/Write Control State Diagram
Current State (n)
Next State (n + 1)
Transition
Input Command Code
Key
n
n+1
n+2
n+3
相關(guān)PDF資料
PDF描述
GS8170DW72AGC-300IT 256K X 72 STANDARD SRAM, 1.8 ns, PBGA209
GS8182S18GBD-200I 1M X 18 DDR SRAM, 0.45 ns, PBGA165
GS8182T36BGD-333IT 512K X 36 DDR SRAM, 0.45 ns, PBGA165
GS82032AGQ-133IT 64K X 32 CACHE SRAM, 10 ns, PQFP100
GS8321EV18GE-133T 2M X 18 CACHE SRAM, 8.5 ns, PBGA165
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS8170DW72AC-300I 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 1.8V 18MBIT 256KX72 1.8NS 209FBGA - Trays
GS8170DW72AC-350I 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 1.8V 18MBIT 256KX72 1.7NS 209FBGA - Trays
GS8170DW72AGC-250 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 1.8V 18MBIT 256KX72 2.1NS 209FBGA - Trays
GS8170DW72AGC-250I 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 1.8V 18MBIT 256KX72 2.1NS 209FBGA - Trays
GS8170DW72AGC-300 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 1.8V 18MBIT 256KX72 1.8NS 209FBGA - Trays