參數(shù)資料
型號: GS8170DW72AC-250IT
廠商: GSI TECHNOLOGY
元件分類: SRAM
英文描述: 256K X 72 STANDARD SRAM, 2.1 ns, PBGA209
封裝: 14 X 22 MM, 1 MM PITCH, BGA-209
文件頁數(shù): 29/32頁
文件大?。?/td> 1038K
代理商: GS8170DW72AC-250IT
GS8170DW36/72AC-350/333/300/250
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04 4/2005
6/32
2003, GSI Technology
Double Late Write
Double Late Write means that Data In is required on the third rising edge of clock. Double Late Write is used to implement
Pipeline mode NBT SRAMs.
Byte Write Control
The Byte Write Enable inputs (Bx) determine which bytes will be written. Any combination of Byte Write Enable control pins,
including all or none, may be activated. A Write Cycle with no Byte Write inputs active is a write abort cycle.
Example of x36 Byte Write Truth Table
Function
W
Ba
Bb
Bc
Bd
Read
H
X
Write Byte A
L
H
Write Byte B
L
H
L
H
Write Byte C
L
H
L
H
Write Byte D
L
H
L
Write all Bytes
L
Write Abort
L
H
SigmaRAM Double Late Write with Pipelined Read
ADV
DD
Read
Write
Read
Write
Read
CD
F
E
CK
Address
A
B
/E1
/W
DQ
QA
CQ
Key
QC
Hi-Z
Access
DB
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GS8170DW72AGC-300IT 256K X 72 STANDARD SRAM, 1.8 ns, PBGA209
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS8170DW72AC-300I 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 1.8V 18MBIT 256KX72 1.8NS 209FBGA - Trays
GS8170DW72AC-350I 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 1.8V 18MBIT 256KX72 1.7NS 209FBGA - Trays
GS8170DW72AGC-250 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 1.8V 18MBIT 256KX72 2.1NS 209FBGA - Trays
GS8170DW72AGC-250I 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 1.8V 18MBIT 256KX72 2.1NS 209FBGA - Trays
GS8170DW72AGC-300 制造商:GSI Technology 功能描述:SRAM SYNC OCTAL 1.8V 18MBIT 256KX72 1.8NS 209FBGA - Trays