參數(shù)資料
型號(hào)： GS8150V36AB-300IT
廠商： GSI TECHNOLOGY
元件分類： SRAM
英文描述： 512K X 36 LATE-WRITE SRAM, 1.6 ns, PBGA119
封裝： FBGA-119
文件頁(yè)數(shù)： 1/25頁(yè)
文件大?。?/td> 885K
代理商： GS8150V36AB-300IT
GS8150V18/36AB-357/333/300/250
1M x 18, 512K x 36
18Mb Register-Register Late Write SRAM
250 MHz–357 MHz
1.8
V VDD
1.5 V or 1.8 V HSTL I/O
119-Bump BGA
Commercial Temp
Industrial Temp
Rev: 1.08 9/2008
1/25
2003, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Features
Register-Register Late Write mode, Pipelined Read mode
1.8 V +150/–100 mV core power supply
1.5 V or 1.8 V HSTL Interface
ZQ controlled programmable output drivers
Dual Cycle Deselect
Fully coherent read and write pipelines
Byte write operation (9-bit bytes)
Differential HSTL clock inputs, K and K
Asynchronous output enable
Sleep mode via ZZ
IEEE 1149.1 JTAG-compliant Serial Boundary Scan
JEDEC-standard 119-bump BGA package
RoHS-compliant 119-bump BGA package available
Family Overview
GS8150V18/36A are 18,874,368-bit (18Mb) high
performance SRAMs. This family of wide, very low voltage
HSTL I/O SRAMs is designed to operate at the speeds needed
to implement economical high performance cache systems.
Functional Description
Because GS8150V18/36A are synchronous devices, address
data inputs and read/write control inputs are captured on the
rising edge of the input clock. Write cycles are internally self-
timed and initiated by the rising edge of the clock input. This
feature eliminates complex off-chip write pulse generation
required by asynchronous SRAMs and simplifies input signal
timing.
GS8150V18/36A support pipelined reads utilizing a rising-
edge-triggered output register. They also utilize a Dual Cycle
Deselect (DCD) output deselect protocol.
GS8150V18/36A are implemented with high performance
HSTL technology and are packaged in a 119-bump BGA.
Mode Control
There are two mode control select pins (M1 and M2), which
allow the user to set the correct read protocol for the design.
The GS8150V18/36A support single clock Pipeline mode,
which directly affects the two mode control select pins. In
order for the part to fuction correctly, and as specified, M1
must be tied to VSS and M2 must be tied to VDD or VDDQ.
This must be set at power-up and should not be changed during
operation.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High)
of the ZZ signal, or by stopping the clock (CK). Memory data is
retained during Sleep mode.
Parameter Synopsis
-357
-333
-300
-250
Unit
Pipeline
Cycle
tKHQV
2.8
1.4
3.0
1.5
3.3
1.6
4.0
2.0
ns
Curr (x18)
Curr (x36)
600
650
550
600
500
550
450
500
mA
相關(guān)PDF資料
PDF描述
GS816032T-250T 512K X 32 CACHE SRAM, 5.5 ns, PQFP100
GS816036BGT-300 512K X 36 CACHE SRAM, 5.3 ns, PQFP100
GS816037T-133I 512K X 36 CACHE SRAM, 3.5 ns, PQFP100
GS8160E18AT-300 1M X 18 CACHE SRAM, 5 ns, PQFP100
GS8160V18AGT-150IT 1M X 18 CACHE SRAM, 7.5 ns, PQFP100
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS8150V36AB-333 制造商:GSI Technology 功能描述:GS8150V36AB-333 - Trays
GS8150V36AB-333I 制造商:GSI 制造商全稱:GSI Technology 功能描述:1M x 18, 512K x 36 18Mb Register-Register Late Write SRAM
GS8150V36AB-357 制造商:GSI Technology 功能描述:GS8150V36AB-357 - Trays
GS8150V36AB-357I 制造商:GSI 制造商全稱:GSI Technology 功能描述:1M x 18, 512K x 36 18Mb Register-Register Late Write SRAM
GS8150V36AGB-250 制造商:GSI 制造商全稱:GSI Technology 功能描述:1M x 18, 512K x 36 18Mb Register-Register Late Write SRAM
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