參數(shù)資料
型號： GS81302T18E-350T
廠商： GSI TECHNOLOGY
元件分類： SRAM
英文描述： 8M X 18 DDR SRAM, 0.45 ns, PBGA165
封裝： 15 X 17 MM, 1 MM PITCH, FPBGA-165
文件頁數(shù)： 34/36頁
文件大?。?/td> 1243K
代理商： GS81302T18E-350T
GS81302T08/09/18/36E-375/350/333/300/250
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03 4/2011
7/36
2011, GSI Technology
Background
Common I/O SRAMs, from a system architecture point of view, are attractive in read dominated or block transfer applications.
Therefore, the SigmaDDR-II SRAM interface and truth table are optimized for burst reads and writes. Common I/O SRAMs are
unpopular in applications where alternating reads and writes are needed because bus turnaround delays can cut high speed
Common I/O SRAM data bandwidth in half.
Burst Operations
Read and write operations are "burst" operations. In every case where a read or write command is accepted by the SRAM, it will
respond by issuing or accepting two beats of data, executing a data transfer on subsequent rising edges of K and K, as illustrated in
the timing diagrams. It is not possible to stop a burst once it starts. Two beats of data are always transferred. This means that it is
possible to load new addresses every K clock cycle. Addresses can be loaded less often, if intervening deselect cycles are inserted.
Deselect Cycles
Chip Deselect commands are pipelined to the same degree as read commands. This means that if a deselect command is applied to
the SRAM on the next cycle after a read command captured by the SRAM, the device will complete the two beat read data transfer
and then execute the deselect command, returning the output drivers to high-Z. A high on the LD pin prevents the RAM from
loading read or write command inputs and puts the RAM into deselect mode as soon as it completes all outstanding burst transfer
operations.
SigmaDDR-II Burst of 2 SRAM Read Cycles
The SRAM executes pipelined reads. The status of the Address, LD and R/W pins are evaluated on the rising edge of K. The read
command (LD low and R/W high) is clocked into the SRAM by a rising edge of K. After the next rising edge of K, the SRAM
produces data out in response to the next rising edge of C (or the next rising edge of K, if C and C are tied high). The second beat
of data is transferred on the next rising edge of C, for a total of two transfers per address load.
SigmaDDR-II Burst of 2 SRAM Write Cycles
The status of the Address, LD and R/W pins are evaluated on the rising edge of K. The SRAM executes "late write" data transfers.
Data in is due at the device inputs on the rising edge of K following the rising edge of K clock used to clock in the write command
(LD and R/W low) and the write address. To complete the remaining beat of the burst of two write transfer, the SRAM captures
data in on the next rising edge of K, for a total of two transfers per address load.
相關PDF資料
PDF描述
GS81302T10E-350I 16M X 9 DDR SRAM, 0.45 ns, PBGA165
GS81302T110E-450T 16M X 9 DDR SRAM, 0.37 ns, PBGA165
GS816136CGD-250T 512K X 36 CACHE SRAM, 5.5 ns, PBGA165
GS8161EV32BD-200 512K X 32 CACHE SRAM, 6.5 ns, PBGA165
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相關代理商/技術參數(shù)
參數(shù)描述
GS81302T36GE-333 制造商:GSI Technology 功能描述:SRAM SYNC SGL 1.8V 144MBIT 4MX36 0.45NS 165FPBGA - Trays
GS81302T36GE-333I 制造商:GSI Technology 功能描述:SRAM SYNC SGL 1.8V 144MBIT 4MX36 0.45NS 165FPBGA - Trays
GS815018AB 制造商:GSI 制造商全稱:GSI Technology 功能描述:1M x 18, 512K x 36 18Mb Register-Register Late Write SRAM
GS815018AB-250 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 2.5V 18MBIT 1MX18 2NS 119FPBGA - Trays
GS815018AB-250I 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 2.5V 18MBIT 1MX18 2NS 119FPBGA - Trays
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