參數(shù)資料
型號(hào)： GS81302D37GE-400I
廠商： GSI TECHNOLOGY
元件分類： SRAM
英文描述： 4M X 36 DDR SRAM, 0.45 ns, PBGA165
封裝： 15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165
文件頁(yè)數(shù)： 32/33頁(yè)
文件大小： 687K
代理商： GS81302D37GE-400I
Preliminary
GS81302D07/10/19/37E-450/400/350/333/300
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.03 12/2010
8/33
2008, GSI Technology
Power-Up Sequence for SigmaQuad-II+ SRAMs
For compatibility across all vendors it is recommended that SigmaQuad-II+ SRAMs must be powered-up in a specific sequence in
order to avoid undefined operations.
Power-Up Sequence
1. Power-up and maintain Doff at Low state.
1a. Apply VDD.
1b. Apply VDDQ.
1c. Apply VREF (may also be applied at the same time as VDDQ).
2. After voltages are within specification range, and clocks (K, K) are stablized, change Doff to High.
3. An additional 2048 clock cycles are required to lock the DLL after it has been enabled.
Note: The DLL may be reset by driving the Doff pin Low or by stopping the K clocks for at least 30 ns. 2048 cycles of clean
K clocks are always required to relock the DLL after it has been stabilized.
DLL Constraints
The DLL synchronizes to either K clock. These clocks should have Low phase jitter (tKVar).
The DLL cannot operate at a frequency lower than that specified by the tKHKH maximum specification for the desired
operating clock frequency.
If the incoming clock is not stablized when DLL is enabled, the DLL may lock on the wrong frequency and cause
undefined errors or failures during the initial stage.
Note:
If the frequency is changed, DLL reset is required. After reset, a minimum of 2048k is required for DLL lock.
Special Functions
Byte Write and Nybble Write Control
Byte Write Enable pins are sampled at the same time that Data In is sampled. A High on the Byte Write Enable pin associated with
a particular byte (e.g., BW0 controls D0–D8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be
stored at the current address at that byte location undisturbed. Any or all of the Byte Write Enable pins may be driven High or Low
during the data in sample times in a write sequence.
Each write enable command and write address loaded into the RAM provides the base address for a 4-beat data transfer. The x18
version of the RAM, for example, may write 72 bits in association with each address loaded. Any 9-bit byte may be masked in any
write sequence.
Nybble Write (4-bit) control is implemented on the 8-bit-wide version of the device. For the x8 version of the device, “Nybble
Write Enable” and “NWx” may be substituted in all the discussion above.
相關(guān)PDF資料
PDF描述
GS81302D10E-300I 16M X 9 DDR SRAM, 0.45 ns, PBGA165
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GS81302T10E-350I 16M X 9 DDR SRAM, 0.45 ns, PBGA165
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