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| 型號： | GMZAN3L |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | XGA ALALOG INTERFACE LCD MONITOR CONTROLLER |
| 中文描述： | ALALOG的XGA液晶顯示器接口控制器 |
| 文件頁數(shù)： | 4/53頁 |
| 文件大?。?/td> | 556K |
| 代理商： | GMZAN3L |
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gmZAN3 Preliminary Data Sheet
C0523-DAT-01G
12
July 2003
Ge nes i s Microc hip Confid e n tia l
http:// w ww . g enesis-mic r ochip.com
3 gmZAN3 Pin List
I/O Legend: A = Analog, I = Input, O = Output, P = Power, G = Ground, I-PU = Input with pull-up,
I-PD = Input with pull down, IO-PD = Bidirectional with pull down
Table 1.
Analog Input Port (Common to gmZAN3T and gmZAN3L)
Pin Name
No.
I/O
Description
AVDD_RED_3.3
96
AP
Analog power (3.3V) for the red channel. Must be bypassed with decoupling capacitor
(0.1F) to AGND_RED pin on system board (as close as possible to the pin).
RED+
97
AI
Positive analog input for Red channel.
RED-
98
AI
Negative analog input for Red channel.
AGND_RED
99
AG
Analog ground for the red channel.
Must be directly connected to the system ground plane.
AVDD_GREEN_3.3
91
AP
Analog power (3.3V) for the green channel. Must be bypassed with decoupling capacitor
(0.1F) to AGND_GREEN pin on system board (as close as possible to the pin).
SOG_MCSS
92
AI
Dedicated Sync-on-Green pin
GREEN+
93
AI
Positive analog input for Green channel.
GREEN-
94
AI
Negative analog input for Green channel.
AGND_GREEN
95
AG
Analog ground for the green channel.
Must be directly connected to the system ground plane.
AVDD_BLUE_3.3
87
AP
Analog power (3.3V) for the blue channel. Must be bypassed with decoupling capacitor
(0.1F) to AGND_BLUE pin on system board (as close as possible to the pin).
BLUE+
88
AI
Positive analog input for Blue channel.
BLUE-
89
AI
Negative analog input for Blue channel.
AGND_BLUE
90
AG
Analog ground for the blue channel.
Must be directly connected to the system ground plane.
AVDD_ADC_3.3
100
AP
Analog power (3.3V) for ADC analog blocks that are shared by all three channels. Includes
band gap reference, master biasing and full-scale adjust. Must be bypassed with
decoupling capacitor (0.1F) to AGND_ADC pin on system board (as close as possible to
the pin).
ADC_TEST
101
AO
Analog test output for ADC. Do not connect.
AGND_ADC
102
AG
Analog ground for ADC analog blocks that are shared by all three channels. Includes band
gap reference, master biasing and full-scale adjust.
Must be directly connected to system ground plane.
GND_ADC
103
AG
Digital ground for ADC clocking circuit.
Must be directly connected to the system ground plane.
VDD_ADC_1.8
104
P
Digital power (1.8V) for ADC encoding logic. Must be bypassed with decoupling capacitor
(0.1F) to GND_ADC pin on system board (as close as possible to the pin).
HSYNC
85
I
ADC input horizontal sync input. The input hysteresis can be set to 0.5V or 1.5V
[Input, Schmitt trigger, 5V-tolerant]
VSYNC
86
I
ADC input vertical sync input. The input hysteresis can be set to 0.5V or 1.5V
[Input, Schmitt triggered, 5V-tolerant]
Table 2.
Clock Pins (Common to gmZAN3T and gmZAN3L)
Pin Name
No
I/O Description
TCLK
111
AI
Reference clock (TCLK) from the 14.3MHz crystal oscillator (see Figure 5), or from single-
ended CMOS/TTL clock oscillator (see Figure 8). This is a 5V-tolerant input. See Table 14.
XTAL
110
AO
Crystal oscillator output.
VBUFS_RPLL
107
AO
Reserved. For test purposes only. Do not connect
AVSS_RPLL
108
G
Analog ground for the reference DDS PLL. Must be directly connected to the system ground
plane.
VSS_RPLL
105
G
Digital ground for the RCLK and clock generator. Must be directly connected to the system
ground plane.
VDD_RPLL_1.8
106
P
Digital power for the RCLK and clock generators. Connect to 1.8V supply. Must be bypassed
with a 0.1Fcapacitor to pin AVSS_RPLL
AVDD_RPLL_3.3
109
P
Analog power for the reference DDS PLL. Connect to 3.3V supply. Must be bypassed with a
0.1Fcapacitor to pin VSS_RPLL
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