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參數(shù)資料
| 型號(hào)： | GMZAN3L |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | XGA ALALOG INTERFACE LCD MONITOR CONTROLLER |
| 中文描述： | ALALOG的XGA液晶顯示器接口控制器 |
| 文件頁數(shù)： | 15/53頁 |
| 文件大小： | 556K |
| 代理商： | GMZAN3L |
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gmZAN3 Preliminary Data Sheet
C0523-DAT-01G
22
July 2003
Ge nes i s Microc hip Confid e n tia l
http:// w ww . g enesis-mic r ochip.com
Figure 7.
Sources of Parasitic Capacitance
Some attention must be given to the details of the oscillator circuit when used with a crystal resonator.
The PCB traces should be as short as possible. The value of Cload that is specified by the manufacturer
should not be exceeded because of potential start up problems with the oscillator. Additionally, the crystal
should be a parallel resonate-cut and the value of the equivalent series resistance must be less then 90
Ohms.
4.1.2 Using an External Clock Oscillator
Another option for providing the reference clock is to use a single-ended external clock oscillator. When
the gmZAN3 is in reset, the state of the HDATA2/AD2/OSC_SEL is sampled. If the pin is left
unconnected (internal pull-down) then external oscillator mode is enabled. In this mode the internal
oscillator circuit is disabled and the external oscillator signal that is connected to the TCLK pin is routed
to an internal clock buffer. This is illustrated in Figure 8.
Vdd
GND
Oscillator
Internal
Oscillator
Reset State Logic
HDATA2/AD2/OSC_SEL
XTAL
TCLK
14 to 24 MHz
Vdd
OSC_OUT
TCLK Distribution
Internal Pull Down
Resistor
~ 60 K
Disable
gmZAN3
111
110
126
External Oscillator Enable
10K
(OPTIONAL)
Figure 8.
Using an External Single-ended Clock Oscillator
Table 12.
TCLK Specification
Frequency
12 to 24 MHz
Jitter Tolerance
250 ps
Rise Time (10% to 90%)
5 ns
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