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參數(shù)資料
| 型號(hào)： | GD16368B-52BA |
| 英文描述： | ATM/SONET Demultiplexer |
| 中文描述： | ATM機(jī)/ SONET的多路解復(fù)用器 |
| 文件頁(yè)數(shù)： | 7/14頁(yè) |
| 文件大?。?/td> | 122K |
| 代理商： | GD16368B-52BA |
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Pin List, GD16367B
Mnemonic:
Pin No.:
Pin Type:
Description:
SOP, SON
6, 7
LVPECL-OUT
Serial differential data output.
CKO, CKN
9, 10
LVPECL-OUT
Differential 140/155 or 280/311 MHz clock out, selected by SEL1.
DIN0, DIN1, DIN2,
DIN3, DIN4, DIN5,
DIN6, DIN7
38, 37, 36,
34, 33, 31,
30, 29
CMOS-IN
2, 4 or 8-bit wide data input. DIN0 is transferred as the first bit, fol-
lowed by DIN1, ....
DICK
41
CMOS-OUT
70/78, 34/39 or 17/19 MHz clock output selected by PW1 and
PW2.
CKR0, CKR1
20, 21
CMOS-IN
Reference clock inputs for the clock synthesis.
CKR0: 70/78 MHz, CKR1: 17/19 MHz.
CKR0 can be used for forward clocking (70/78 MHz) in 2-bit
mode.
SEL1
45
CMOS-IN
When low the CMI encoder is enabled and CKO/CKN is
280/311 MHz. When high, data is passed unchanged (NRZ
mode) and CKO/CKN is 140/155 MHz.
SEL4
25
CMOS-IN
When high CKR1 is used as reference for the PLL. When low
CKR0 is used.
SEL2, SEL3
23, 24
CMOS-IN
DINx input phase versus DICK/CKRx select:
SEL3
SEL2
0
0
T
DEL
= 0
°
1
1
T
DEL
= 90
°
1
0
T
DEL
= 180
°
0
1
T
DEL
= 270
°
CKRU
42
CMOS-OUT
70/78 MHz clock output. May be used as input to the GD16368B
CKRF pin.
CLOF
18
ANL
Ext. Loop filter pin. Connect 2.2
μ
F in series with 680
from this
pin to the VEEA pin.
LLSIP, LLSIN
48, 47
LVPECL-IN
Line loop-back serial differential data, 140/155 MHz.
To be connected from LLSOP/LLSON of the GD16368B.
LLCIP, LLCIN
51, 50
LVPECL-IN
Line loop-back serial differential clock, 140/155 Mbit/s.
To be connected from LLCOP/LLCON of the GD16368B.
LLB
49
CMOS-IN
When high, Line loop-back is enabled.
SLSOP, SLSON
4, 3
LVPECL-OUT
Switch loop-back serial differential data, 140/155 Mbit/s.
To be connected to SLSIP/SLSIN of the GD16368B.
SLB
2
CMOS-IN
When high, switch loop-back is enabled.
PW1, PW2
44, 43
CMOS-IN
Parallel port width / parallel clock rate:
PW2
PW1
0
0
2 bit, DIN0..DIN1 - DICK = 70/78 MHz
0
1
4 bit, DIN0..DIN3 - DICK = 35/38 MHz
1
0
8 bit, DIN0..DIN7 - DICK = 17/19 MHz
1
1
Not valid
ICV
28
CMOS-IN
Insert Code Violation. When shifted high, one violation is inserted
(“1" level toggled).
TCK
12
ANL-IN
Test clock input - for test purpose only. Connect to VEEA for nor-
mal operation.
SELTCK
14
ANL-IN
Test clock enable - for test purpose only. Connect to VDD for nor-
mal operation.
VDD
5, 8, 11, 22, 26, 32,
35, 40, 46, 52
PWR
3.3 V power.
VDDA
16, 19
PWR
5 V power for VCO.
VEE
1, 13, 27, 39
PWR
0 V power.
VEEA
15
PWR
0 V power for VCO.
NC
17
No Connected.
Data Sheet Rev. 14
GD16367B/GD16368B
Page 7 of 14
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