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參數(shù)資料
| 型號(hào)： | GD16368B-52BA |
| 英文描述： | ATM/SONET Demultiplexer |
| 中文描述： | ATM機(jī)/ SONET的多路解復(fù)用器 |
| 文件頁(yè)數(shù)： | 3/14頁(yè) |
| 文件大?。?/td> | 122K |
| 代理商： | GD16368B-52BA |
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Functional Details, The Transmitter - GD16367B
The GD16367B is the encoder/transmit-
ter (
see Figure 1
) with:
u
Multiplexer (2/4/8:1)
u
Selectable CMI-Encoding
u
NRZ/CMI data and clock differential
outputs
u
Selectable System Loop Back data
differential output
u
Selectable Line Loop Back data and
clock differential inputs
Multiplexer
The parallel input data (DIN0...DIN7) are
received by the multiplexer. This is done
synchronously with the DICK output
clock, which is used when counter clock-
ing. Counter clocking allows 2:1, 4:1 ,
and 8:1 multiplexing. Forward clocking is
only possible when operating in the 2:1
mode.
A low noise reference clock is recom-
mended, as the clock noise within the
PLL loop bandwidth is transmitted as jit-
ter on the serial outputs. The 70/78 MHz
clock input (CKR0) is selected when
SEL4 is low. The 17/19 MHz clock input
(CKR1) is selected when SEL4 is high.
For PDH system rates 17 or 70 MHz is
used. For SDH system rates 19 or
78 MHz is used.
Figure 1.
Block Diagram - GD16367B
Counter Clocking
The output clock (DICK) is used for
clocking out the parallel system data into
the MUX. The frequency of DICK de-
pends on the reference clock and the
multiplexing mode (See Table 1 on
page
2
). Four phases timing relation between
DINx and DICK are provided by the
SEL2 and SEL3 (See AC Characteristics
on
page 11
, and Pin List on
page 7
).
Forward Clocking
When operated in 2:1 multiplexing mode,
a forward clocking scheme can be used:
u
Set PW1=PW2=SEL4=0
u
Connect the forwarded 70/78 MHz
clock to CKR0.
The control inputs (SEL2 and SEL3) con-
trol the timing relation between DINx and
CKR0, see pin list on
page 7
.
CMI-Encoder
When the CMI-encoding is enabled
(SEL1=0), every bit of the 140/155 Mbit/s
output from the multiplexer is encoded to
a 2-bit CMI-word, resulting in a 280/
311 Mbit/s output of the CMI-encoder;
and a 280/311 MHz clock (CKO/CKN)
from the CMI-encoder. See the CMI-
coding in Table 2.
NRZ:
CMI
:
Note
:
0
01
consecutive NRZ zeros
“0000..” gives
“01010101...” as
CMI-output
1
00/11 consecutive NRZ ones
“1111...” gives
“00110011...” as
CMI-output
Table 2
CMI Coding.
When the CMI-encoding is disabled
(SEL1=1), the 140/155 Mbit/s output from
the multiplexer is passed through the
CMI-encoder; and a 140/155 MHz clock
(CKO/CKN) is generated from the
CMI-encoder.
Data Sheet Rev. 14
GD16367B/GD16368B
Page 3 of 14
P
P
I
S
L
L
L
L
C
2.2 F
680
V
L
S
VEE
VDD
VDDA
SLSOP
SLSON
SOP
SON
CKO
CKN
CKRU
DICK
SEL4
Clock
Synth.
MUX
CMI
Encoder
SEL3
SEL2
CKR1
CKR0
DIN7
DIN0
SELTCK
TCK
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