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參數(shù)資料
| 型號： | GD16368B-52BA |
| 英文描述： | ATM/SONET Demultiplexer |
| 中文描述： | ATM機(jī)/ SONET的多路解復(fù)用器 |
| 文件頁數(shù)： | 12/14頁 |
| 文件大?。?/td> | 122K |
| 代理商： | GD16368B-52BA |
General
Symbol:
Characteristic:
Conditions:
MIN.:
TYP.:
MAX.:
UNIT:
T
A
DOCK to DOUx Valid
1
ns
T
B
DOCK to DOUx Valid
Note 1
T/4 + 1
ns
T
C
DOCK to DOUx Valid
Note 1
T/2 + 1
ns
T
D
DOCK to DOUx Valid
Note 1
3*T/4 + 1
ns
T
CO
CKO to SOP/SON Valid
Note 2
0.5
ns
T
LLCO
LLCOP to LLSOP/N Valid
0.3
ns
T
SA
Set-up Time before DICK
1
ns
T
SB
Set-up Time after DICK
Note 3
T/4 - 1
ns
T
SC
Set-up Time after DICK
Note 3
T/2 - 1
ns
T
SD
Set-up Time after DICK
Note 3
3*T/4 - 1
ns
T
HA
Hold Time after DICK
1
ns
T
HB
Hold Time after DICK
Note 3
T/4 + 1
ns
T
HC
Hold Time after DICK
Note 3
T/2 + 1
ns
T
HD
Hold Time after DICK
Note 3
3*T/4 + 1
ns
R
Duty
Duty Cycle, CKR0/1, CKRF
Note 4
40/60
60/40
%
D
CKRF
CRKF Frequency Deviation from Nominal Line
Frequency
-200
+200
ppm
F
VCO
VCO Frequency Range
136
158
MHz
T
Acq-PU
Acquisition Time, GD16367B/368B
Power up
100
μ
s
μ
s
T
Acq-INT
Acquisition Time, GD16368B
Inp. Interrupt
10
L
CID
Number of Consecutive Identical Digits,
GD16368B
>120
Units
T
R-LVPECL
LVPECL Rise Time
Note 5
800
ps
T
F-LVPECL
LVPECL Fall Time
Note 5
800
ps
T
R-CMOS
CMOS Rise Time
Note 6
5
ns
T
F-CMOS
CMOS Fall Time
Note 6
3
ns
Note 1:
Note 2:
T equals the period time of DOCK (one bit period).
Also valid for LLB operation. The typical LLB data & clock delay difference for the GD16367B
(
T
LLSIP
SOP/N
- T
LLCOP/N
CKO/N
) is 0.2 ns. As the
T
LLCO
of the GD16368B (LLCOP to LLSOP/N) is 0.3 ns (typ.), the resulting
T
CO
in LLB mode mode is 0.5 ns = 0.3 ns (GD16367B) + 0.2 ns (GD16368B).
T equals the period time of DICK (one bit period).
Duty cycle measured at
V
TH
= 1.4 V
20 - 80 %, 50
to
V
DD
-2.0 V
20 - 80 %, 10 pF and 100
μ
A load. Typically,
T
R
= 0.5 ns + C x 0.4 ns/pF;
T
F
= 1 ns + C x 0.16 ns/pF.
Note 3:
Note 4:
Note 5:
Note 6:
Data Sheet Rev. 14
GD16367B/GD16368B
Page 12 of 14
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|---|---|
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