參數(shù)資料
型號(hào)： FMS9875KGC100
文件頁(yè)數(shù)： 20/29頁(yè)
文件大?。?/td> 481K
代理商： FMS9875KGC100
PRODUCT SPECIFICATION
FMS9875
20
REV. 1.2.15 1/14/02
After each byte is read, the pointer auto-increments to allow
multiple data byte transfers within one read cycle.
Preceding each slave write, there must be a start cycle.
Following the pointer byte there should be a stop cycle.
After the last read, there must be a stop cycle comprising
a LOW-to-HIGH transition of SDA while SCL is HIGH.
(see Figure 18, right waveform)
A repeated start signal occurs when the master device driv-
ing the serial interface generates a start signal without first
generating a stop signal to terminate the current communica-
tion. This is used to change the mode of communication
(read, write) between the slave and master without releasing
the serial interface lines.
Serial Interface Read/Write Examples
Examples below show how serial bus cycles can be linked
together for multiple register read and write access cycles.
For sequential register accesses, each ACK handshake ini-
tiates further SCL clock cycles from the master to transfer
the next data byte.
Write to one register
1.
Start signal
2.
Slave Address byte (R/W bit = LOW)
3.
Pointer byte
4.
Data byte to base address
5.
Stop signal
Write to four consecutive registers
1.
Start signal
2.
Slave Address byte (R/W bit = LOW)
3.
Pointer byte
4.
Data byte to base address
5.
Data byte to (base address + 1)
6.
Data byte to (base address + 2)
7.
Data byte to (base address + 3)
8.
Stop signal
Read from one register
1.
Start signal
2.
Slave Address byte (R/W bit = LOW)
3.
Pointer byte (= base address)
4.
Stop signal (optional)
5.
Start signal
6.
Slave Address byte (R/W bit = HIGH)
7.
Data byte from base address
8.
Stop signal
Read from four registers
1.
Start signal
2.
Slave Address byte (R/W bit = LOW)
3.
Pointer byte (= base address)
4.
Stop signal (optional)
5.
Start signal
6.
Slave Address byte (R/W bit = HIGH)
7.
Data byte from base address
8.
Data byte from (base address + 1)
9.
Data byte from (base address + 2)
10. Data byte from (base address + 3)
11. Stop signal
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