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參數(shù)資料
| 型號(hào)： | FAN6921MLMY |
| 廠商： | Fairchild Semiconductor |
| 文件頁數(shù)： | 20/23頁 |
| 文件大?。?/td> | 1764K |
| 描述： | IC CTLR PFC/FLYBACK 16-SOICN |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 模式： | 臨界傳導(dǎo)（CRM） |
| 電流 - 啟動(dòng)： | 10µA |
| 電源電壓： | 8.5 V ~ 25 V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC N |
| 包裝： | 帶卷 (TR) |
?2010 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN6921ML " Rev. 1.0.3
20
Protection for PWM Stage
VDD Pin Over-Voltage Protection (OVP)
V
DD
over-voltage protection is used to prevent device
damage once V
DD
voltage is higher than device stress
rating voltage. In case of V
DD
OVP, the controller stops
all switching operation immediately and enters latch-off
mode until the AC plug is removed.
Adjustable Over-Temperature Protection and
Externally Latch Triggering (RT Pin)
Figure 43 is a typical application circuit with an internal
block of RT pin. As shown, a constant current I
RT
flows
out from the RT pin, so the voltage V
RT
on RT pin can
be obtained as I
RT
current multiplied by the resistor,
which consists of NTC resistor and R
A
resistor. If the RT
pin voltage is lower than 0.8 V and lasts for a debounce
time, latch mode is activated and stops all PFC and
PWM switching.
The RT pin is usually used to achieve over-temperature
protection with a NTC resistor and provides external
latch triggering for additional protection. Engineers can
use an external triggering circuit (e.g. transistor) to pull
low the RT pin and activate controller latch mode.
Generally, the external latch triggering needs to activate
rapidly since it is usually used to protect power system
from abnormal conditions. Therefore, the protection
debounce time of the RT pin is set to around 100 祍
once RT pin voltage is lower than 0.5 V.
For over-temperature protection, because the
temperature would not change immediately; the RT pin
voltage is reduced slowly as well. The debounce time
for adjustable OTP should not need a fast reaction. To
prevent improper latch triggering on the RT pin due to
exacting test conditions (e.g. lightning test); when the
RT pin triggering voltage is higher than 0.5 V, the
protection debounce time is set to around 10ms. To
avoid improper triggering on the RT pin, it is
recommended to add a small value capacitor (e.g.
1000 pF) paralleled with NTC and R
A
resistor.
Latched
0.8V
RT
I
RT
=100礎(chǔ)
FAN6921
Adjustable Over-
Temperature protection&
External Latch triggering
NTC
R
RT
12
0.5V
Debounce
time
110祍
10ms
Figure 43. Adjustable Over-Temperature Protection
Output Over-Voltage Protection (DET Pin)
Referring to Figure 44, during the discharge time of
PWM transformer inductor; the voltage across on
auxiliary winding is reflected from secondary winding
and therefore the flat voltage on the DET pin is
proportional to the output voltage. FAN6921ML can
sample this flat voltage level after a t
OFF
blanking time to
perform output over-voltage protection. This t
OFF
blanking time is used to ignore the voltage ringing from
leakage inductance of PWM transformer. The sampled
flat voltage level is compared with internal threshold
voltage 2.5 V and, once the protection is activated,
FAN6921ML enters latch mode.
The controller can protect rapidly by this kind of cycle-
by-cycle sampling method in the case of output over
voltage. The protection voltage level can be determined
by the ratio of external resistor divider R
A
and R
DET
. The
flat voltage on DET pin can be expressed by the
following equation:
(
)
A
DET
A
S
O
DET
A
R
N N V
R
R
=
?nbsp ?/DIV>
+
(2)
A
D
E
T
A
A
O
R
R
R
N
N
+
?/DIV>
?/DIV>
V
D E T
P W M
G a t e
V
A U X
P
A
O
N
N
V
F
C
?/DIV>
_
0 . 3 V
t
O F F
b l a n k i n g
s a m p l i n g
h e r e
A
O
N
N
?/DIV>
t
t
t
Figure 44. Operation Waveform of Output
Over-Voltage Detection
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