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參數(shù)資料
| 型號： | FAN6921MLMY |
| 廠商： | Fairchild Semiconductor |
| 文件頁數(shù)： | 19/23頁 |
| 文件大小： | 1764K |
| 描述： | IC CTLR PFC/FLYBACK 16-SOICN |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 模式： | 臨界傳導(dǎo)（CRM） |
| 電流 - 啟動： | 10µA |
| 電源電壓： | 8.5 V ~ 25 V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC N |
| 包裝： | 帶卷 (TR) |
?2010 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN6921ML " Rev. 1.0.3
19
0.3V
I
DET
Auxiliary
Winding
DET
FAN6921
+
V
AUX
-
+
V
DET
-
10
R
A
R
DET
Figure 39. Valley Detection
tOFF
Start to
detect valley
I
DET
flow out
from DET pin
Delay, then
trigger gate
signal
Valley
switching
0V
0V
V
AUX
V
DET
OPWM
Figure 40. Measured Waveform of Valley Detection
High / Low Line Over-Power Compensation (DET Pin)
Generally, when the power switch turns off, there is a
delay from gate signal falling edge to power switch off.
This delay is produced by an internal propagation delay
of the controller and the turn-off delay of the PWM
switch due to gate resistor and gate-source capacitor
C
ISS
of PWM switch. At different AC input voltage, this
delay time produces different maximum output power
under the same PWM current limit level. Higher input
voltage generates higher maximum output power since
applied voltage on primary winding is higher and causes
higher rising slope inductor current. It results in higher
peak inductor current at the same delay. Furthermore,
under the same output wattage, the peak switching
current at high line is lower than at low line. Therefore,
to make the maximum output power close at different
input voltages, the controller needs to regulate V
LIMIT
of
the CSPWM pin to control the PWM switch current.
Referring to Figure 41, during the on time of the PWM
switch, the input voltage is applied to primary winding
and the voltage across on auxiliary winding, V
AUX
, is
proportional to primary winding voltage. As the input
voltage increases, the reflected voltage on auxiliary
winding V
AUX
rises as well. FAN6921ML also clamps the
DET pin voltage and flows out a current I
DET
. Since the
current, I
DET
, is in accordance with V
AUX
, FAN6921ML
can depend on this current I
DET
during PWM on time to
regulate the current limit level of the PWM switch to
perform high / low line over-power compensation.
As the input voltage increases, the reflected voltage on
the auxiliary winding, V
AUX
, becomes higher (as well as
the current I
DET
) and the controller regulates the V
LIMIT
to
a lower level.
The R
DET
resistor is connected from auxiliary winding to
the DET pin. Engineers can adjust this R
DET
resistor to
get proper V
LIMIT
voltage to fit power system needs. The
characteristic curve of I
DET
current vs. V
LIMIT
voltage on
CSPWM pin is shown in Figure 42.
(
)
DET
IN
A
P
DET
V N N
R
=
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
(1)
where V
IN
is input voltage; N
A
is turn number of auxiliary
winding; and N
P
is turn number of primary winding.
0 V
0 V
t
OF F
t
O N
V
A U X
= - [ V
IN
" ( N a /N p ) ]
D E T p i n v o l t a g e i s c l a m p e d
d u r i n g t
O N
t i m e p e r i o d
V
A U X
V
D E T
O P W M
Figure 41. Relationship between V
AUX
and V
IN
0
1 0 0
2 0 0
3 0 0
4 0 0
5 0 0
6 0 0
3 0 0
4 0 0
5 0 0
6 0 0
7 0 0
8 0 0
9 0 0
I
DE T
A
Figure 42. I
DET
Current vs. V
LIMIT
Voltage
Characteristic Curve
Leading-Edge Blanking (LEB)
When the PFC or PWM switches are turned on, a
voltage spike is induced on the current-sense resistor
due to the reciprocal effect by reverse recovery energy
of the output diode and C
OSS
of power MOSFET. To
prevent this spike, a leading-edge blanking time is built-
in and a small RC filter is recommended between the
CSPWM pin and GND (e.g. 100 ? 470 pF).
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