參數(shù)資料
型號: FAN6921MLMY
廠商: Fairchild Semiconductor
文件頁數(shù): 11/23頁
文件大小: 1764K
描述: IC CTLR PFC/FLYBACK 16-SOICN
標準包裝: 2,500
模式: 臨界傳導(CRM)
電流 - 啟動: 10µA
電源電壓: 8.5 V ~ 25 V
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 16-SOIC(0.154",3.90mm 寬)
供應商設備封裝: 16-SOIC N
包裝: 帶卷 (TR)
 
?2010 Fairchild Semiconductor Corporation
 
www.fairchildsemi.com
FAN6921ML " Rev. 1.0.3
11
Electrical Characteristics (Continued)
V
DD
=15 V, T
A
=-40~105 (T
A
=T
J
), unless otherwise specified.
Symbol
Parameter
Conditions
Min.
Typ.
Max.     Units
PWM Output Section
V
CLAMP
 
PWM Gate Output Clamping
Voltage
V
DD
=25 V
16.0
17.5
19.0
V
V
OL
 
PWM Gate Output Voltage Low     V
DD
= 15 V, Io=100 mA
 
 
1.5
V
V
OH
 
PWM Gate Output Voltage High    V
DD
= 15 V, Io=100 mA
8
 
 
V
t
R
 
PWM Gate Output Rising Time
C
L
=3 nF,
V
DD
=12 V, 20~80%
 
80
110
ns
t
F
 
PWM Gate Output Falling Time
C
L
=3 nF,
V
DD
=12 V, 20~80%
 
40
70
ns
Current Sense Section
t
PD
 
Delay to Output
 
150
200
ns
V
LIMIT
 
The Limit Voltage on CSPWM
Pin for Over Power
Compensation
I
DET
< 75 礎, T
A
=25癈
0.81
0.84
0.87
V
I
DET
=185 礎, T
A
=25癈
0.69
0.72
0.75
I
DET
=350 礎, T
A
=25癈
0.55
0.58
0.61
I
DET
=550 礎, T
A
=25癈
0.34
0.40
0.46
V
SLOPE
 
Slope Compensation
(4)
 
t
ON
=45 祍,
RANGE=Open
0.25
0.30
0.35
V
t
ON
=0 祍
0.05
0.10
0.15
 
t
ON-BNK
 
Leading-Edge Blanking Time
 
300
 
ns
V
CS-FLOATING
 
CSPWM Pin Floating V
CSPWM
 
Clamped High Voltage
CSPWM Pin Floating
4.5
 
5
V
t
CS-H
 
Delay Once CSPWM Pin Floating CSPWM Pin Floating
 
150
 
RT Pin Over-Temperature Protection Section
T
OTP
 
Internal Threshold Temperature
for OTP
(4)
 
125
140
155
T
OTP-HYST
 
Hysteresis Temperature for
Internal OTP
(4)
 
 
30
 
I
RT
 
Internal Source Current of RT Pin
90
100
110
V
RT-LATCH
     Latch-Mode Triggering Voltage
0.75
0.80
0.85
V
V
RT-RE-LATCH
   Latch-Mode Release Voltage
V
RT-LATCH
+0.15
V
RT-LATCH
+0.20
V
RT-LATCH
+0.25
V
V
RT-OTP-LEVEL
 
Threshold Voltage for Two-level
Debounce Time
0.45
0.50
0.55
V
t
RT-OTP-H
 
Debounce Time for OTP
 
10
 
ms
t
RT-OTP-L
 
Debounce Time for Externally
Triggering
V
RT
<V
RT-OTP-LEVEL
 
70
100
130
Note:
4.    Guaranteed by design.
 
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