參數(shù)資料
型號： FAN6921MLMY
廠商： Fairchild Semiconductor
文件頁數(shù)： 15/23頁
文件大?。?/td> 1764K
描述： IC CTLR PFC/FLYBACK 16-SOICN
標(biāo)準(zhǔn)包裝： 2,500
模式： 臨界傳導(dǎo)（CRM）
電流 - 啟動(dòng)： 10µA
電源電壓： 8.5 V ~ 25 V
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 16-SOIC（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 16-SOIC N
包裝： 帶卷 (TR)
 
?2010 Fairchild Semiconductor Corporation
 
www.fairchildsemi.com
FAN6921ML " Rev. 1.0.3
15
Functional Description
PFC Stage
Multi-Vector Error Amplifier and THD Optimizer
For   better   dynamic   performance,   faster   transient
response,   and   precise   clamping   on   PFC   output,
FAN6921ML uses a transconductance type amplifier
with proprietary innovative multi-vector error amplifier.
The schematic diagram of this amplifier is shown in
Figure 25. The PFC output voltage is detected from the
INV pin by an external resistor divider circuit that
consists of R
1
  and R
2
. When PFC output variation
voltage reaches 6% over or under the reference voltage
of 2.5 V, the multi-vector error amplifier adjusts its output
sink or source current to increase the loop response to
simplify the compensated circuit.
C
CO  M  P
3
2
F A N 6 9 2 1
C o
I N V
2 . 5 V
2 . 3 5 V
2 . 6 5 V
E r r o r
A m  p lif ie r
P F C
V o
C O  M  P
R
1
R
2
 
Figure 25. Multi-Vector Error Amplifier
The feedback voltage signal on the INV pin is compared
with reference voltage 2.5 V, which makes the error
amplifier source or sink current to charge or discharge
its   output   capacitor   C
COMP
.   The   COMP   voltage   is
compared   with   the   internally   generated   sawtooth
waveform to determine the on time of PFC gate.
Normally, with lower feedback loop bandwidth, the
variation of the PFC gate on time should be very small
and   almost   constant   within   one   input   AC   cycle.
However, the power factor correction circuit operating at
light-load   condition   has   a   defect   (zero   crossing
distortion) that distorts input current and makes the
systems Total Harmonic Distortion (THD) worse. To
improve   the   result   of   THD   at   light-load   condition,
especially at high input voltage, an innovative THD
optimizer is inserted by sampling the voltage across the
current-sense   resistor.   This   sampling   voltage   on
current-sense   resistor   is   added   into   the   sawtooth
waveform to modulate the on time of PFC gate, so it is
not constant on time within a half AC cycle. The method
of operation between THD optimizer and PWM is shown
in Figure 26. After THD optimizer processes, around the
valley of AC input voltage, the compensated on time
becomes wider than the original. The PFC on time,
which is around the peak voltage, is narrowed by the
THD optimizer. The timing sequences of the PFC MOS
and the shape of the inductor current are shown in
Figure 27. Figure 28 shows the difference between
calculated fixed on time and fixed on time with THD
optimizer during a half AC cycle.
4
3
2 .5 V
IN V
P F C V
O
E rro r
A m p lifie r
V
C  O  M  P
R S
F ilp -F lo p
C S P F C
P F C
M O S
R
S
F A N 6 9 2 1
S a w to o th
G e n e ra to r
T H D
O p tim iz e r
R
1
R
2
 
Figure 26. Multi-Vector Error Amplifier with
THD Optimizer
 
I
L, A  V  G  
( f ix e d O n - T im  e )
I
L , A  V  G
( w it h T H D O p t im  iz e r )
O N
O F F
G a te S ig n a l
w ith
T H D O p tim iz e r
V
CO  M  P
S a w to o th
G a te S ig n a l
w ith F ix e d
 
Figure 27. Operation Waveforms of Fixed On Time
with and without THD Optimizer
 
0
0.0014    0.0028    0.0042    0.0056    0.0069    0.0083
0
0.3
0.6
0.9
1.2
1.5
1.8
Fixed O n-tim e w ith T H D O ptim izer
Fixed O n tim e
Input C urrent
Tim e (Seconds)
P
O
 : 9 0 W
In p u t V o lta g e : 9 0 V A C
P F C In d u cto r : 4 6 0 m H
C S R esisto r : 0 .1 5 W
 
Figure 28. Calculated Waveforms of Fixed On Time
with and without THD Optimizer During a Half
AC Cycle
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