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參數(shù)資料
| 型號： | FAB2210UCX |
| 廠商： | Fairchild Semiconductor |
| 文件頁數(shù)： | 20/26頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SUBSYSTEM HDPH AMP G 20-WLCSP |
| 標準包裝： | 1 |
| 類型： | D 類；G 類 |
| 輸出類型： | 1-通道（單聲道），帶立體聲耳機 |
| 在某負載時最大輸出功率 x 通道數(shù)量： | 3.3W x 1 @ 8 歐姆; 29mW x 2 @ 32 歐姆 |
| 電源電壓： | 2.8 V ~ 5.25 V |
| 特點： | 消除爆音，差分輸入，I²C，靜音，短路和熱保護，關機，音量控制 |
| 安裝類型： | 表面貼裝 |
| 供應商設備封裝： | 20-WLCSP |
| 封裝/外殼： | 20-UFBGA，WLCSP |
| 包裝： | 標準包裝 |
| 其它名稱： | FAB2210UCXFSDKR |
35
9614A–AT42–08/10
AT42QT2161
Shared X line GPOs are always outputs. By default, the dedicated GPIOs are set as inputs.
Make sure to drive (set to outputs) these GPIOs if not used, as floating pins may consume
unnecessary current.
Default: 0 (All inputs)
6.24
Address 74 – 75: GPIO/GPO PWM
Setting the corresponding GPIO PWM bit to 1 will enable PWM on the respective pin. The pin
will be driven according to the duty cycle specified in PWM Level (address 76).
PWM will only be enabled on GPIOs that have their GPIO direction set to 1 (output).
Shared X line GPOs will only be driven when not performing any measurements. During
measurements, burst pulses will be driven from the X lines. Ensure that any connected device
will not be affected.
All PWM enabled GPIOs/GPOs will only be switched when not doing any measurements.
Therefore, the PWM duty cycle’s accuracy will depend on the burst lengths of keys, as the
longer the burst length, the longer the periods of no PWM switching.
Default: 0 (PWM disabled)
6.25
Address 76: PWM Level
This sets the Duty Cycle of the PWM enabled pins. Valid values are between 0 – 255. There is a
constant level band at either end of the range, so:
A value of 0 – 10 gives a 100 percent low output
A value of 250 – 255 gives a 100 percent high output
Default: 0 (100 percent low output)
Table 6-25.
GPIO/GPO PWM
Address
b7b6b5
b4b3b2b1
b0
74
X7
X6
X5
X4
X3
X2
X1
X0
75
0
GPIO3
GPIO2
GPIO1
0
Table 6-26.
PWM Level
Address
b7b6b5
b4b3b2b1
b0
76
DUTY_CYC
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