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參數(shù)資料
| 型號： | FAB2210UCX |
| 廠商： | Fairchild Semiconductor |
| 文件頁數(shù)： | 10/26頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SUBSYSTEM HDPH AMP G 20-WLCSP |
| 標準包裝： | 1 |
| 類型： | D 類；G 類 |
| 輸出類型： | 1-通道（單聲道），帶立體聲耳機 |
| 在某負載時最大輸出功率 x 通道數(shù)量： | 3.3W x 1 @ 8 歐姆; 29mW x 2 @ 32 歐姆 |
| 電源電壓： | 2.8 V ~ 5.25 V |
| 特點： | 消除爆音，差分輸入，I²C，靜音，短路和熱保護，關機，音量控制 |
| 安裝類型： | 表面貼裝 |
| 供應商設備封裝： | 20-WLCSP |
| 封裝/外殼： | 20-UFBGA，WLCSP |
| 包裝： | 標準包裝 |
| 其它名稱： | FAB2210UCXFSDKR |
26
9614A–AT42–08/10
AT42QT2161
6.4
Address 2: General Status
These bits indicate the general status of the device. A change in this byte will cause the
CHANGE line to trigger.
RESET: this bit is set after a reset. This bit is clear after this byte is read back by the host.
CYCLE OVERRUN: this bit is set if the cycle time is more than 16 ms. It will be cleared when the
cycle time is less than 16 ms.
Note: holding any of the I2C-compatible lines, for clock stretching or other purposes, will
increase the cycle time.
CC: this common change bit is set if all the selected keys (address 78 – 79) have a signal
change of more than half the detection threshold, NTHR. The CC bit is not debounced.
This bit can be used to indicate a common change in signals, e.g. In a notebook application,
where the cover is closing, so that the host can suppress key detections.
Note: the CC bit will be set to 1 if no keys are selected to be in the Common Change group (see
SDET: this bit is set if a touch is detected on the slider.
6.5
Address 3 – 4: Key Status
Address 3: detect status for keys 0 to 7
Address 4: detect status for keys 8 to 15
Each location indicates all keys in detection, if any, as a bitfield; touched keys report as “1”,
untouched or disabled keys report as “0”. A change in this byte will cause the CHANGE line to
trigger.
Table 6-4.
General Status
Address
b7b6b5
b4b3b2b1
b0
2
RESET
CYCLE
OVER
RUN
0
CC
SDET
Table 6-5.
Key Status and Numbering
Address
b7b6b5
b4b3b2b1
b0
3
k7
k6k5k4k3
k2k1k0
4
k15
k14
k13
k12
k11
k10
k9
k8
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