參數(shù)資料
型號： EVAL-ADV7180LQEBZ
廠商： Analog Devices Inc
文件頁數(shù)： 9/116頁
文件大?。?/td> 0K
描述： BOARD EVALUATION ADV7180
標(biāo)準(zhǔn)包裝： 1
系列： Advantiv®
主要目的： 視頻，SDTV 視頻解碼器 - NTSC，PAL，SECAM
嵌入式： 否
已用 IC / 零件： ADV7180
主要屬性： CVBS（復(fù)合），Y/C（S 視頻）和 YPrPb（元件）輸入
次要屬性： 8 位 ITU-R BT.656 YCrCb 4:2:2 輸出
已供物品： 板
相關(guān)產(chǎn)品： ADV7180BCPZ-REEL-ND - IC VIDEO DECODER SDTV 40-LFCSP
ADV7180BSTZ-ND - IC VIDEO DECODER SDTV 64-LQFP
ADV7180BCPZ-ND - IC VIDEO DECODER SDTV 40-LFCSP
ADV7180
Data Sheet
Rev. I | Page 106 of 116
Interrupt and VDP Map
Bit
(Shading Indicates
Default State)
Address Register
Bit Description
7 6 5 4 3 2 1 0
Comments
Notes
0x86
VDP_GS_VPS_PDC_UTC_2
(read only)
GS_VPS_PDC_UTC_BYTE_2[7:0]
x x x x x x x x
Decoded Gemstar/VPS/PDC/UTC data
0x87
VDP_GS_VPS_PDC_UTC_3
(read only)
GS_VPS_PDC_UTC_BYTE_3[7:0]
x x x x x x x x
Decoded Gemstar/VPS/PDC/UTC data
0x88
VDP_VPS_PDC_UTC_4
(read only)
VPS_PDC_UTC_BYTE_4[7:0]
x x x x x x x x
Decoded VPS/PDC/UTC data
0x89
VDP_VPS_PDC_UTC_5
(read only)
VPS_PDC_UTC_BYTE_5[7:0]
x x x x x x x x
Decoded VPS/PDC/UTC data
0x8A
VDP_VPS_PDC_UTC_6
(read only)
VPS_PDC_UTC_BYTE_6[7:0]
x x x x x x x x
Decoded VPS/PDC/UTC data
0x8B
VDP_VPS_PDC_UTC_7
(read only)
VPS_PDC_UTC_BYTE_7[7:0]
x x x x x x x x
Decoded VPS/PDC/UTC data
0x8C
VDP_VPS_PDC_UTC_8
(read only)
VPS_PDC_UTC_BYTE_8[7:0]
x x x x x x x x
Decoded VPS/PDC/UTC data
0x8D
VDP_VPS_PDC_UTC_9
(read only)
VPS_PDC_UTC_BYTE_9[7:0]
x x x x x x x x
Decoded VPS/PDC/UTC data
0x8E
VDP_VPS_PDC_UTC_10
(read only)
VPS_PDC_UTC_BYTE_10[7:0]
x x x x x x x x
Decoded VPS/PDC/UTC data
0x8F
VDP_VPS_PDC_UTC_11
(read only)
VPS_PDC_UTC_BYTE_11[7:0]
x x x x x x x x
Decoded VPS/PDC/UTC data
0x90
VDP_VPS_PDC_UTC_12
(read only)
VPS_PDC_UTC_BYTE_12[7:0]
x x x x x x x x
Decoded VPS/PDC/UTC data
0x92
VDP_VITC_DATA_0
(read only)
VITC_DATA_0[7:0]
x x x x x x x x
Decoded VITC data
0x93
VDP_VITC_DATA_1
(read only)
VITC_DATA_1[7:0]
x x x x x x x x
Decoded VITC data
0x94
VDP_VITC_DATA_2
(read only)
VITC_DATA_2[7:0]
x x x x x x x x
Decoded VITC data
0x95
VDP_VITC_DATA_3
(read only)
VITC_DATA_3[7:0]
x x x x x x x x
Decoded VITC data
0x96
VDP_VITC_DATA_4
(read only)
VITC_DATA_4[7:0]
x x x x x x x x
Decoded VITC data
0x97
VDP_VITC_DATA_5
(read only)
VITC_DATA_5[7:0]
x x x x x x x x
Decoded VITC data
0x98
VDP_VITC_DATA_6
(read only)
VITC_DATA_6[7:0]
x x x x x x x x
Decoded VITC data
0x99
VDP_VITC_DATA_7
(read only)
VITC_DATA_7[7:0]
x x x x x x x x
Decoded VITC data
0x9A
VDP_VITC_DATA_8
(read only)
VITC_DATA_8[7:0]
x x x x x x x x
Decoded VITC data
0x9B
VDP_VITC_CALC_CRC
(read only)
VITC_CRC[7:0]
x x x x x x x x
Decoded VITC CRC data
0x9C
VDP_OUTPUT_SEL
Reserved
0 0 0 0
WSS_CGMS_CB_CHANGE
0
Disable content-based updating of
CGMS and WSS data
The available bit shows
the availability of data
only when its content
has changed
1
Enable content-based updating of
CGMS and WSS data
GS_VPS_PDC_UTC_CB_CHANGE
0
Disable content-based updating of
Gemstar, VPS, PDC, and UTC data
1
Enable content-based updating of
Gemstar, VPS, PDC, and UTC data
I2C_GS_VPS_PDC_UTC[1:0]
0 0
Gemstar_1×/Gemstar_2×
Standard expected to
be decoded
0 1
VPS
1 0
PDC
1 1
UTC
1
Shading indicates default values.
2
x indicates a bit that keeps the last written value.
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