參數(shù)資料
型號(hào)： EVAL-ADV7180LQEBZ
廠商： Analog Devices Inc
文件頁數(shù)： 4/116頁
文件大?。?/td> 0K
描述： BOARD EVALUATION ADV7180
標(biāo)準(zhǔn)包裝： 1
系列： Advantiv®
主要目的： 視頻，SDTV 視頻解碼器 - NTSC，PAL，SECAM
嵌入式： 否
已用 IC / 零件： ADV7180
主要屬性： CVBS（復(fù)合），Y/C（S 視頻）和 YPrPb（元件）輸入
次要屬性： 8 位 ITU-R BT.656 YCrCb 4:2:2 輸出
已供物品： 板
相關(guān)產(chǎn)品： ADV7180BCPZ-REEL-ND - IC VIDEO DECODER SDTV 40-LFCSP
ADV7180BSTZ-ND - IC VIDEO DECODER SDTV 64-LQFP
ADV7180BCPZ-ND - IC VIDEO DECODER SDTV 40-LFCSP
Data Sheet
ADV7180
Rev. I | Page 101 of 116
Interrupt and VDP Map
Bit
(Shading Indicates
Default State)
Address Register
Bit Description
7 6 5 4 3 2 1 0
Comments
Notes
0x45
Raw Status 2
(read only)
CCAPD
0
No CCAPD data detected—
VBI System 2
These bits are status
bits only; they cannot be
cleared or masked;
Register 0x46 is used for
this purpose
1
CCAPD data detected—VBI System 2
Reserved
x x x
EVEN_FIELD
0
Current SD field is odd numbered
1
Current SD field is even numbered
Reserved
x x
MPU_STIM_INTRQ
0
MPU_STIM_INTRQ = 0
1
MPU_STIM_INTRQ = 1
0x46
Interrupt Status 2
(read only)
CCAPD_Q
0
Closed captioning not detected in the
input video signal—VBI System 2
These bits can be cleared
or masked by Register 0x47
and Register 0x48, res-
pectively; note that the
interrupt in Register 0x46
for the CCAP, Gemstar,
CGMS, and WSS data uses
the Mode 1 data slicer
1
Closed captioning data detected in the
video input signal—VBI System 2
GEMD_Q
0
Gemstar data not detected in the input
video signal—VBI System 2
1
Gemstar data detected in the input
video signal—VBI System 2
Reserved
x x
SD_FIELD_CHNGD_Q
0
SD signal has not changed field from
odd to even or vice versa
1
SD signal has changed Field from odd to
even or vice versa
Reserved
x
Not used
Reserved
x
Not used
MPU_STIM_INTRQ_Q
0
Manual interrupt not set
1
Manual interrupt set
0x47
Interrupt Clear 2
(write only)
CCAPD_CLR
0
Do not clear—VBI System 2
Note that interrupt in
Register 0x46 for the
CCAP, Gemstar, CGMS,
and WSS data uses the
Mode 1 data slicer
1
Clears CCAPD_Q bit—VBI System 2
GEMD_CLR
0
Do not clear
1
Clears GEMD_Q bit
Reserved
0 0
SD_FIELD_CHNGD_CLR
0
Do not clear
1
Clears SD_FIELD_CHNGD_Q bit
Reserved
x x
Not used
MPU_STIM_INTRQ_CLR
0
Do not clear
1
Clears MPU_STIM_INTRQ_Q bit
0x48
Interrupt Mask 2
(read/write)
CCAPD_MSK
0
Masks CCAPD_Q bit—VBI System 2
Note that interrupt in
Register 0x46 for the
CCAP, Gemstar, CGMS,
and WSS data uses the
Mode 1 data slicer
1
Unmasks CCAPD_Q bit—VBI System 2
GEMD_MSK
0
Masks GEMD_Q bit—VBI System 2
1
Unmasks GEMD_Q bit—VBI System 2
Reserved
0 0
Not used
SD_FIELD_CHNGD_MSK
0
Masks SD_FIELD_CHNGD_Q bit
1
Unmasks SD_FIELD_CHNGD_Q bit
Reserved
0 0
Not used
MPU_STIM_INTRQ_MSK
0
Masks MPU_STIM_INTRQ_Q bit
1
Unmasks MPU_STIM_INTRQ_Q bit
0x49
Raw Status 3
(read only)
SD_OP_50Hz; SD 60 Hz/50 Hz
frame rate at output
0
SD 60 Hz signal output
These bits are status
bits only; they cannot be
cleared or masked;
Register 0x4A is used for
this purpose
1
SD 50 Hz signal output
SD_V_LOCK
0
SD vertical sync lock not established
1
SD vertical sync lock established
SD_H_LOCK
0
SD horizontal sync lock not established
1
SD horizontal sync lock established
Reserved
x
Not used
SCM_LOCK
0
SECAM lock not established
1
SECAM lock established
Reserved
x x x
Not used
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