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參數(shù)資料
| 型號(hào)： | EVAL-ADF4193EBZ1 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 17/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION EB1 FOR ADF4193 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計(jì)時(shí)，頻率合成器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADF4193 |
| 主要屬性： | 單路分?jǐn)?shù)-N PLL |
| 次要屬性： | 13MHz PFD 圖形用戶界面 |
| 已供物品： | 板，線纜，軟件 |
| 相關(guān)產(chǎn)品： | ADF4193BCPZ-ND - IC PLL FREQ SYNTHESIZER 32LFCSP ADF4193BCPZ-RL7-ND - IC PLL FREQ SYNTHESIZER 32LFCSP ADF4193BCPZ-RL-ND - IC PLL FREQ SYNTHESIZER 32LFCSP |
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ADF4193
Data Sheet
Rev. F | Page 24 of 32
switches opened, and thus the phase swing that occurs when the
BW is reduced can be minimized.
With dither off, the fractional spur pattern due to the SDM’s
quantization noise also depends on the phase word the modulator
is seeded with. Tables of optimized FRAC and phase values for
popular SW1/SW2 and ICP timer settings can be down-loaded
from the ADF4193 product page. If making use of a phase table,
first write phase to double buffered Register R2, then write the
INT and FRAC to R0.
Avoiding Integer Boundary Channels
A further option when programming a new frequency involves
a write to Register R1 to avoid integer boundary spurs. If it is
found that the integer boundary spur level is too high, an
option is to move the integer boundary away from the desired
channel by reprogramming the R divider to select a different
PFD frequency. For example, if REFIN = 104 MHz and R = 4 for
a 26 MHz PFD frequency and MOD = 130 for 200 kHz steps,
the frequency channel at 910.2 MHz has a 200 kHz integer
boundary spur because it is 200 kHz offset from 35 × 26 MHz.
An alternative way to synthesize this channel is to set R = 5 for a
20.8 MHz PFD reference and MOD = 104 for 200 kHz steps.
The 910.2 MHz channel is now 5 MHz offset from the nearest
integer multiple of 20.8 MHz and the 5 MHz beat note spurs are
well attenuated by the loop. Setting double buffered Bit R1 [23] = 1
(CP ADJ bit) increases the charge pump current by 25%, which
compensates for the 25% increase in N with the change to the
20.8 MHz PFD frequency. This maintains constant loop dynamics
and settling time performance for jumps between the two PFD
frequencies. The CP ADJ bit should be cleared again when jumping
back to 26 MHz-based channels.
The Register R1 settings necessary for integer boundary spur
avoidance are all double buffered and do not become active on
the chip until the next write to Register R0. Register R0 should
always be the last register written to when programming a new
frequency.
Serial Interface Activity
The serial interface activity when programming the R2 or R1
registers causes no noticeable disturbance to the synthesizers
settled phase or degradation in its frequency spectrum. Therefore,
in a GSM application, it can be performed during the active
part of the data burst. Because it takes just 10.2 s to program
the three registers, R2, R1, and R0, with the 6.5 MHz serial
interface clock rate typically used, this programming can also be
performed during the previous guard period with the LE edge
to latch in the R0 data delayed until it’s time to switch
frequency.
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參數(shù)描述 |
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| EVAL-ADF4193EBZ2 | 功能描述:BOARD EVALUATION EB2 FOR ADF4193 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081 |
| EVAL-ADF4206-7EB1 | 制造商:Analog Devices 功能描述:EVALUATION BOARD FOR DUAL RF PLL FREQUENCY SYNTHESIZERS 制造商:Analog Devices 功能描述:DUAL RF PLL FREQ SYNTHESIZERS - Bulk |
| EVAL-ADF4208EB1 | 制造商:Analog Devices 功能描述:Evaluation Board For Dual RF PLL Frequency Synthesizers 制造商:Analog Devices 功能描述:DUAL RF PLL FREQ SYNTHESIZERS - Bulk |
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