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參數資料
| 型號： | EVAL-ADF4193EBZ1 |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 16/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION EB1 FOR ADF4193 |
| 標準包裝： | 1 |
| 主要目的： | 計時，頻率合成器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADF4193 |
| 主要屬性： | 單路分數-N PLL |
| 次要屬性： | 13MHz PFD 圖形用戶界面 |
| 已供物品： | 板，線纜，軟件 |
| 相關產品： | ADF4193BCPZ-ND - IC PLL FREQ SYNTHESIZER 32LFCSP ADF4193BCPZ-RL7-ND - IC PLL FREQ SYNTHESIZER 32LFCSP ADF4193BCPZ-RL-ND - IC PLL FREQ SYNTHESIZER 32LFCSP |
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Data Sheet
ADF4193
Rev. F | Page 23 of 32
The 8:1 loop bandwidth switching ratio of the ADF4193 makes
it possible to attenuate all spurs to sufficiently low levels for most
applications. The final loop BW can be chosen to ensure that all
spurs are far enough out of band while meeting the lock time
requirements with the 8× bandwidth boost.
The ADF4193 programmable modulus and R divider can also
be used to avoid integer boundary channels. This option is
described in the Avoiding Integer Boundary Channels section.
Reference Spurs
Reference spurs are generally not a problem in fractional-N
synthesizers as the reference offset is far outside the loop
bandwidth. However, any reference feedthrough mechanism
that bypasses the loop can cause a problem. One such mechanism
is feedthrough of low levels of on-chip reference switching noise
out through the RFIN pin back to the VCO, resulting in reference
spur levels as high as –90 dBc. These spurs can be suppressed
below –110 dBc by inserting sufficient reverse isolation, for
example, through an RF buffer between the VCO and RFIN pin.
In addition, care should be taken in the PCB layout to ensure
that the VCO is well separated from the input reference to avoid
a possible feedthrough path on the board.
POWER-UP INITIALIZATION
After applying power to the ADF4193, a 14-step sequence is
recommended, as described in Table 8.
The divider and timer setting used in the example in Table 8 is
for a DCS1800 Tx synthesizer with a 104 MHz REFIN frequency.
Table 8. Power-Up Initialization Sequence
Step
Register
Bits
Hex
Codes
Description
1
R5 [7:0]
FD
Set all power-down bits.
2
R3 [15:0]
005B
PD polarity = 1, ground CPOUT+/
CPOUT–.
Wait
10 ms
Allow time for loop filter
capacitors to discharge.
3
R7 [15:0]
0007
Clear test modes.
4
R6 [15:0]
000E
Initialize PLL modes, digital lock
detect on MUXOUT.
5
R6 [15:0]
900E
10 ns lock detect threshold,
digital lock detect on MUXOUT.
6
R4 [23:0]
004464
SW1/SW2 timer = 10.8 s.
7
R4 [23:0]
00446C
SW3 timer = 10.8 s.
8
R4 [23:0]
004394
ICP timer = 8.6 s.
9
R2 [15:0]
00D2
Phase = 26.
10
R1 [23:0]
520209
8/9 prescaler, doubler disabled,
R = 4, toggle FF on, MOD = 65.
11
R0 [23:0]
480140
INT = 144, FRAC = 40 for
1880 MHz output frequency.
12
R3 [15:0]
007B
PD polarity = 1, release CPOUT+/
CPOUT–.
13
R5 [7:0]
05
Clear all power-down bits.
14
R0 [23:0]
480140
INT = 144, FRAC = 40 for
1880 MHz output frequency.
The ADF4193 powers up after Step 13. It locks to the programmed
channel frequency after Step 14.
CHANGING THE FREQUENCY OF THE PLL AND THE
PHASE LOOK-UP TABLE
Once the ADF4193 is initialized, a write to Register R0 is all that is
required to program a new output frequency. The N divider is
updated with the values of INT and FRAC on the next PFD cycle
following the LE edge that latches in the R0 word. However, the
settling time and spurious performance of the synthesizer can
be further optimized by modifying R1 and R2 register settings
on a channel-by-channel basis. These settings are double buffered
by the write to R0. This means that while the data is loaded in
through the serial interface on the respective R1 and R2 write
cycles, the synthesizer is not updated with their data until the
next write to Register R0.
The R2 register can be used to digitally adjust the phase of the VCO
output relative to the reference edge. The phase can be adjusted
over the full 360° range at RF with a resolution of 360°/MOD. In
most frequency synthesizer applications, the actual phase offset
of the VCO output with respect to the reference is unknown and
does not matter. In such applications, the phase adjustment
capability of the R2 register can instead be used to optimize the
settling time performance, as described in the Phase Look-Up
Table section.
Phase Look-Up Table
The ADF4193’s fast lock sequence is initiated following the write to
Register R0. The fast lock timers are programmed so that after the
PLL has settled in wide BW mode, the charge pump current is
reduced and loop filter resistor switches are opened to reduce the
loop BW. The reference cycle on which these events occur is
determined by the values preprogrammed into the timeout
counters.
Figure 10 and Figure 13 show that the lock time to final phase is
dominated by the phase swing that occurs when the BW is reduced.
Once the PLL has settled to final frequency and phase, in wide
BW mode, this phase swing is the same, regardless of the size of
the synthesizer’s frequency jump. The amplitude of the phase
swing is related to the current flowing through the loop filter
zero resistors on the PFD reference cycle that the SW1/SW2
switches are opened. In an integer-N PLL, this current is zero
once the PLL has settled. In a fractional-N PLL, the current is
zero on average but varies from one reference cycle to the next,
depending on the quantization error sequence output from the
digital Σ-Δ modulator. Because the Σ-Δ modulator is all digital
logic, clocked at the PFD reference rate, for a given value of MOD,
the actual quantization error on any given reference cycle is
determined by the value of FRAC and the PHASE word that the
modulator is seeded with, following the write to R0. By choosing
an appropriate value of PHASE, corresponding to the value of
FRAC, that is programmed on the next write to R0, the size of
the error current on the PFD reference cycle the SW1/SW2
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