參數(shù)資料
型號: EVAL-AD7887CB
廠商: Analog Devices, Inc.
英文描述: +2.7 V to +5.25 V, Micropower, 2-Channel, 125 kSPS, 12-Bit ADC in 8-Lead uSOIC
中文描述: 2.7 V至5.25 V,微功耗,2通道,125 kSPS的,12位ADC的8引腳uSOIC
文件頁數(shù): 4/16頁
文件大?。?/td> 133K
代理商: EVAL-AD7887CB
REV. B
AD7887
TIMNGSPECIFICATIONS
1
–4–
+4.75 V to +5.25 V
Limit at T
MIN
, T
MAX
(A, B Versions)
Parameter
f
SCLK2
t
CONVERT
t
ACQ
t
1
t
23
t
33
t
4
t
5
t
6
t
7
t
84
t
9
+2.7 V to +3.6 V
Units
Description
2
14.5 t
SCLK
1.5 t
SCLK
10
30
75
20
20
0.4 t
SCLK
0.4 t
SCLK
80
5
2
14.5 t
SCLK
1.5 t
SCLK
10
60
100
20
20
0.4 t
SCLK
0.4 t
SCLK
80
5
MHz max
T hroughput T ime = t
CONVERT
+ t
ACQ
= 16 t
SCLK
CS
to SCLK Setup T ime
Delay from
CS
Until DOUT T hree-State Disabled
Data Access T ime after SCLK Falling Edge
Data Setup T ime Prior to SCLK Rising Edge
Data Valid to SCLK Hold T ime
SCLK High Pulsewidth
SCLK Low Pulsewidth
CS
Rising Edge to DOUT High Impedance
Power-Up T ime from Shutdown
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns max
μ
s typ
NOT ES
1
Sample tested at +25
°
C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 volts.
2
Mark/Space ratio for the SCLK input is 40/60 to 60/40.
3
Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.0 V.
4
t
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. T he measured number is then extrapolated back
to remove the effects of charging or discharging the 50 pF capacitor. T his means that the time, t
8
, quoted in the timing characteristics is the true bus relinquish time of
the part and is independent of the bus loading.
Specifications subject to change without notice.
+1.6V
I
OL
200
m
A
200
m
A
I
OH
TO
OUTPUT
PIN
C
L
50pF
Figure 1. Load Circuit for Digital Output Timing Specifications
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