參數(shù)資料
型號： EVAL-AD7887CB
廠商： Analog Devices, Inc.
英文描述： +2.7 V to +5.25 V, Micropower, 2-Channel, 125 kSPS, 12-Bit ADC in 8-Lead uSOIC
中文描述： 2.7 V至5.25 V，微功耗，2通道，125 kSPS的，12位ADC的8引腳uSOIC
文件頁數(shù)： 2/16頁
文件大?。?/td> 133K
代理商： EVAL-AD7887CB
REV. B
–2–
AD7887–SPECIFICATIONS
1
(V
DD
= +2.7 V to +5.25 V, V
REF
= +2.5 V External/Internal Reference unless otherwse
Parameter
A Version
1
B Version
1
noted, f
SCLK
= 2 MHz; T
A
= T
MN
to T
MAX
, unless otherwse noted.)
Units
T est Conditions/Comments
DYNAMIC PERFORMANCE
Signal to Noise + Distortion
Ratio
2, 3
(SNR)
T otal Harmonic Distortion
2
(T HD)
Peak Harmonic or Spurious Noise
2
Intermodulation Distortion
2
(IMD)
Second Order T erms
T hird Order T erms
Channel-to-Channel Isolation
2
Full Power Bandwidth
71
–80
–80
71
–80
–80
dB typ
dB typ
dB typ
f
IN
= 10 kHz Sine Wave, f
SAMPLE
= 125 kSPS
f
IN
= 10 kHz Sine Wave, f
SAMPLE
= 125 kSPS
f
IN
= 10 kHz Sine Wave, f
SAMPLE
= 125 kSPS
–80
–80
–80
2.5
–80
–80
–80
2.5
dB typ
dB typ
dB typ
MHz typ
fa = 9.983 kHz, fb = 10.05 kHz, f
SAMPLE
= 125 kSPS
fa = 9.983 kHz, fb = 10.05 kHz, f
SAMPLE
= 125 kSPS
f
IN
= 25 kHz
@ 3 dB
DC ACCURACY
Resolution
Integral Nonlinearity
2
Differential Nonlinearity
2
Offset Error
2
Any Channel
12
±
2
±
2
±
3
±
4
±
6
0.5
±
2
±
1
±
6
2
12
±
1
±
1
±
3
±
4
±
6
0.5
±
2
±
1
±
6
2
Bits
LSB max
LSB max
LSB max
LSB max
LSB typ
LSB max
LSB max
LSB max
LSB typ
LSB max
Guaranteed No Missing Codes to 11 Bits (A Grade)
V
DD
= 5 V, Dual-Channel Mode
V
DD
= 3 V, Dual-Channel Mode
Single-Channel Mode
Offset Error Match
2
Gain Error
2
Dual-Channel Mode
Single-Channel Mode, External Reference
Single-Channel Mode, Internal Reference
Gain Error Match
2
ANALOG INPUT
Input Voltage Ranges
Leakage Current
Input Capacitance
0 to V
REF
±
5
20
0 to V
REF
±
5
20
Volts
μ
A max
pF typ
REFERENCE INPUT /OUT PUT
REF
IN
Input Voltage Range
Input Impedance
REF
OUT
Output Voltage
REF
OUT
T empco
2.5/V
DD
10
2.45/2.55
±
50
2.5/V
DD
10
2.45/2.55
±
50
V min/max
k
typ
V min/max
ppm/
°
C typ
Functional from 1.2 V
Very High Impedance If Internal Reference Disabled
LOGIC INPUT S
Input High Voltage, V
INH
2.4
2.1
0.8
±
1
10
2.4
2.1
0.8
±
1
10
V min
V min
V max
μ
A max
pF max
V
DD
= +4.75 V to +5.25 V
V
DD
= +2.7 V to +3.6 V
V
DD
= +2.7 V to +5.25 V
T ypically 10 nA, V
IN
= 0 V or V
DD
Input Low Voltage, V
INL
Input Current, I
IN
Input Capacitance, C
IN4
LOGIC OUT PUT S
Output High Voltage, V
OH
I
SOURCE
= 200
μ
A
V
DD
= +2.7 V to +5.25 V
I
SINK
= 200
μ
A
V
DD
– 0.5
0.4
±
1
10
Straight (Natural) Binary
V
DD
– 0.5
0.4
±
1
10
V min
V max
μ
A max
pF max
Output Low Voltage, V
OL
Floating-State Leakage Current
Floating-State Output Capacitance
5
Output Coding
CONVERSION RAT E
T hroughput T ime
16
16
SCLK Cycles
Conversion T ime + Acquisition T ime 125 kSPS
with 2 MHz Clock
T rack/Hold Acquisition T ime
2
Conversion T ime
1.5
14.5
1.5
14.5
SCLK Cycles
SCLK Cycles
7.25
μ
s (2 MHz Clock)
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參數(shù)描述
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