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參數(shù)資料
| 型號： | EVAL-AD7887CB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | +2.7 V to +5.25 V, Micropower, 2-Channel, 125 kSPS, 12-Bit ADC in 8-Lead uSOIC |
| 中文描述： | 2.7 V至5.25 V，微功耗，2通道，125 kSPS的，12位ADC的8引腳uSOIC |
| 文件頁數(shù)： | 11/16頁 |
| 文件大?。?/td> | 133K |
| 代理商： | EVAL-AD7887CB |
REV. B
AD7887
–11–
MODE S OF OPE RAT ION
T he AD7887 has a number of different modes of operation.
T hese are designed to provide flexible power management op-
tions. T hese options can be chosen to optimize the power dissi-
pation/throughput rate ratio for differing application requirements.
T he modes of operation are controlled by the PM1 and PM0 bits
of the Control Register as previously outlined. For read-only
operation of the AD7887, the default mode of all 0s in the Con-
trol Register can be set up by tying the DIN line permanently
low.
Mode 1 (PM1 = 0, PM0 = 0)
T his mode allows the user to control the powering down of the
part via the
CS
pin. Whenever
CS
is low, the AD7887 is fully
powered up; whenever
CS
is high, the AD7887 is in full shut-
down. When
CS
goes from high to low, all on-chip circuitry
starts to power up. It takes approximately, 5
μ
s for the AD7887
internal circuitry to be fully powered up. As a result, a conver-
sion (or sample-and-hold acquisition) should not be initiated
during this 5
μ
s.
Figure 13 shows a general diagram of the operation of the AD7887
in this mode. T he input signal is sampled on the second rising
edge of SCLK following the
CS
falling edge. T he user should
ensure that 5
μ
s elapses between the falling edge of
CS
and the
second rising edge of SCLK . In microcontroller applications,
this is readily achievable by driving the
CS
input from one of the
port lines and ensuring that the serial data read (from the micro-
controllers serial port) is not initiated for 5
μ
s. In DSP applica-
tions, where the
CS
is generally derived from the serial frame
synchronization line, it is usually not possible to separate the
CS
falling edge and second SCLK rising edge by up to 5
μ
s without
affecting the speed of the rest of the serial clock. T herefore, the
user will need to write to the Control Register to exit this mode
and (by writing PM1 = 0 and PM0 = 1) put the part into Mode
2, i.e., normal mode. A second conversion will then need to be
initiated when the part is powered-up to get a conversion result.
T he write operation which takes place in conjunction with this
second conversion can put the part back into Mode 1 and the
part will go into power-down mode when
CS
returns high.
Mode 2 (PM1 = 0, PM0 = 1)
In this mode of operation, the AD7887 remains fully powered
up regardless of the status of the
CS
line. It is intended for
fastest throughput rate performance as the user does not have to
worry about the 5
μ
s power-up time previously mentioned.
Figure 14 shows the general diagram of the operation of the
AD7887 in this mode.
T he data presented to the AD7887 on the DIN line during the
first eight clock cycles of the data transfer are loaded to the
Control Register. T o continue to operate in this mode, the user
must ensure that PM1 is loaded with 0 and PM0 is loaded with
1 on every data transfer.
T he falling edge of
CS
initiates the sequence and the input
signal is sampled on the second rising edge of the SCLK input.
Sixteen serial clock cycles are required to complete the conver-
sion and access the conversion result. Once a data transfer is
complete (
CS
has returned high), another conversion can be
initiated immediately by bringing
CS
low again.
SCLK
CS
DOUT
DIN
1
16
CONTROL REGISTER DATA IS LOADED ON THE FIRST 8 CLOCKS.
PM1 AND PM0 = 0 TO KEEP THE PART IN THIS MODE
4 LEADING ZEROS + CONVERSION RESULT
DATA IN
THE PART POWERS UP ON
CS
FALLING EDGE AS PM1 AND PM0 = 0
THE PART POWERS DOWN ON
CS
RISING EDGE AS PM1 AND PM0 = 0
Figure 13. Mode 1 Operation
SCLK
CS
DOUT
DIN
THE PART REMAINS POWERED UP
AT ALL TIMES AS
PM1 = 0 AND PM0 = 1
1
16
CONTROL REGISTER DATA IS LOADED ON THE FIRST 8 CLOCKS.
PM1 = 0 AND PM0 = 1 TO KEEP THE PART IN THIS MODE
4 LEADING ZEROS + CONVERSION RESULT
DATA IN
Figure 14. Mode 2 Operation
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| EVAL-AD7887CB4 | 制造商:AD 制造商全稱:Analog Devices 功能描述:2.7 V to 5.25 V, Micropower, 2-Channel, 125 kSPS, 12-Bit ADC in 8-Lead MSOP |
| EVAL-AD7887CBZ | 功能描述:BOARD EVAL FOR AD7887 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 模數(shù)轉換器 (ADC) 系列:* 產(chǎn)品培訓模塊:Obsolescence Mitigation Program 標準包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標準）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
| EVAL-AD7888CB | 制造商:Analog Devices 功能描述:EVAL KIT FOR 2.7 V TO 5.25 V, MICROPWR, 8CH, 125 KSPS, 12-BI - Bulk |
| EVAL-AD7890-2 | 制造商:Analog Devices 功能描述:AD7890 EVAL BOARD |
| EVAL-AD7891-1CB | 制造商:Analog Devices 功能描述:Evaluation Board For LC2MOS 8-Channel, 12-Bit High Speed Data Acquisition System 44PLCC 制造商:Analog Devices 功能描述:EVAL BD FOR LC2MOS 8CH, 12-BIT HS DATA ACQ SYS 44PLCC(P-44A) - Bulk |
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