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參數(shù)資料
| 型號： | EVAL-AD7856CB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 5 V Single Supply, 8-Channel 14-Bit 285 kSPS Sampling ADC |
| 中文描述： | 5 V單電源，8通道14位285 kSPS的采樣ADC |
| 文件頁數(shù)： | 5/32頁 |
| 文件大小： | 294K |
| 代理商： | EVAL-AD7856CB |
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AD7856
–5–
REV. A
TYPICAL TIMING DIAGRAMS
Figures 2 and 3 show typical read and write timing diagrams for
serial Interface Mode 2. The reading and writing occurs after
conversion in Figure 2, and during conversion in Figure 3. To
attain the maximum sample rate of 285 kHz, reading and writ-
ing must be performed during conversion as in Figure 3. At
least 330 ns acquisition time must be allowed (the time from
the falling edge of BUSY to the next rising edge of
CONVST
)
before the next conversion begins to ensure that the part is
settled to the 14-bit level. If the user does not want to provide
the
CONVST
signal, the conversion can be initiated in software
by writing to the control register.
t
CONVERT
= 3.5
m
s MAX, 5.25
m
s MAX FOR K VERSION
t
1
= 100ns MIN,
t
4
= 30/50ns MAX A/K,
t
7
= 30/40ns MIN A/K
DB15
SYNC
(I/P)
SCLK (I/P)
t
3
BUSY (O/P)
CONVST
(I/P)
t
CONVERT
1
5
6
t
10
16
DOUT (O/P)
DB0
DB11
DIN (I/P)
DB15
DB0
THREE-
STATE
DB11
THREE-STATE
t
1
t
2
t
4
t
6
t
6
t
9
t
11
t
12
t
8
t
7
Figure 2. Timing Diagram for Interface Mode 2 (Reading/Writing After Conversion)
DB15
SYNC
(I/P)
SCLK (I/P)
t
3
BUSY (O/P)
CONVST
(I/P)
t
CONVERT
1
5
6
t
10
16
DOUT (O/P)
DB0
DB11
DIN (I/P)
DB15
DB0
THREE-
STATE
DB11
THREE-STATE
t
1
t
2
t
4
t
6
t
6
t
9
t
11
t
12
t
8
t
7
t
CONVERT
= 3.5
m
s MAX, 5.25
m
s MAX FOR K VERSION
t
1
= 100ns MIN,
t
4
= 30/50ns MAX A/K,
t
7
= 30/40ns MIN A/K
Figure 3. Timing Diagram for Interface Mode 2 (Reading/Writing During Conversion)
TO OUTPUT
PIN
C
L
100pF
I
OL
1.6mA
200
m
A
+2.1V
I
OL
Figure 1. Load Circuit for Digital Output Timing
Specifications
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