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參數(shù)資料
| 型號(hào)： | EVAL-AD7856CB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 5 V Single Supply, 8-Channel 14-Bit 285 kSPS Sampling ADC |
| 中文描述： | 5 V單電源，8通道14位285 kSPS的采樣ADC |
| 文件頁(yè)數(shù)： | 25/32頁(yè) |
| 文件大?。?/td> | 294K |
| 代理商： | EVAL-AD7856CB |
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AD7856
–25–
REV. A
Mode 2 (3-Wire SPI/QSPI Interface Mode)
This is the DEFAULT INTERFACE MODE.
In Figure 33 below we have the timing diagram for interface
Mode 2, which is the SPI/QSPI interface mode. Here the
SYNC
input is active low and may be pulsed or permanently tied low.
If
SYNC
is permanently low, 16 clock pulses must be applied to
the SCLK pin for the part to operate correctly otherwise, with a
pulsed
SYNC
input, a continuous SCLK may be applied pro-
vided
SYNC
is low for only 16 SCLK cycles. In Figure 33 the
t
3
= –0.4
t
SCLK
MIN (NONCONTINUOUS SCLK) –/+0.4
t
SCLK
ns MIN/MAX (CONTINUOUS SCLK),
t
6
= 45/75ns MAX (A/K),
t
7
= 30/40ns MIN (A/K),
t
8
= 20ns MIN,
t
11
= 30ns MIN (NONCONTINUOUS SCLK), 30/0.4
t
SCLK
ns MIN/MAX (CONTINUOUS SCLK)
t
11
t
12
16
6
5
4
3
t
10
2
1
t
8
t
6
t
9
t
8
t
6
t
3
t
5
THREE-
STATE
DB0
DB10
DB11
DB12
DB13
DB14
DB15
DB15
DB14
DB13
DB12
DB11
DB10
DB0
SYNC
(I/P)
SCLK (I/P)
DOUT (O/P)
DIN (I/P)
POLARITY PIN LOGIC HIGH
t
7
THREE-
STATE
Figure 33. SPI/QSPI Mode 2 Timing Diagram for Read/Write Operation with DIN Input
DOUT Output and
SYNC
Input
SYNC
going low disables the three-state on the DOUT pin. The
first falling edge of the SCLK after the
SYNC
going low clocks
out the first leading zero on the DOUT pin. The DOUT pin is
three-stated again a time, t
12
, after the
SYNC
goes high. With
the DIN pin the data input has to be set up a time, t
7
, before the
SCLK rising edge as the part samples the input data on the
SCLK rising edge in this case. If resetting the interface is re-
quired, the
SYNC
must be taken high and then low.
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