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參數(shù)資料
| 型號： | EVAL-AD7856CB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 5 V Single Supply, 8-Channel 14-Bit 285 kSPS Sampling ADC |
| 中文描述： | 5 V單電源，8通道14位285 kSPS的采樣ADC |
| 文件頁數(shù)： | 27/32頁 |
| 文件大?。?/td> | 294K |
| 代理商： | EVAL-AD7856CB |
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AD7856
–27–
REV. A
Interface Mode 2 Configuration
Figure 35 shows the flowchart for configuring the part in Inter-
face Mode 2. In this case the read and write operations take
place simultaneously via the serial port. Writing all 0s ensures
APPLY
SYNC
(IF REQUIRED), SCLK, WRITE
TO CONTROL REGISTER SETTING NEXT
CHANNEL, CONVST BIT TO 1, READ
PREVIOUS CONVERSION RESULT ON
DOUT PIN (NOTE 1)
INITIATE
CONVERSION
IN
SOFTWARE
START
POWER-ON, APPLY CLKIN SIGNAL,
WAIT 150ms FOR AUTOMATIC CALIBRATION
PULSE
CONVST
PIN
WAIT FOR BUSY SIGNAL TO GO LOW
OR
WAIT FOR BUSY BIT = 0
NO
SERIAL
INTERFACE
MODE
NO
YES
YES
APPLY
SYNC
(IF REQUIRED), SCLK, READ
CURRENT CONVERSION RESULT ON
DOUT PIN, AND WRITE CHANNEL SELECTION
NOTE 1: WHEN USING THE SOFTWARE CONVERSION START AND TRANSFERRING DATA
DURING CONVERSION, THE USER MUST ENSURE THAT THE CONTROL REGISTER WRITE
OPERATION EXTENDS BEYOND THE FALLING EDGE OF BUSY. THE FALLING EDGE OF
BUSY RESETS THE CONVST BIT TO 0 AND ONLY AFTER THIS TIME CAN IT BE
REPROGRAMMED TO 1 TO START THE NEXT CONVERSION.
WAIT APPROX 200ns AFTER
CONVST
RISING EDGE
APPLY
SYNC
(IF REQUIRED), SCLK, READ
PREVIOUS CONVERSION RESULT ON DOUT
PIN, AND WRITE CHANNEL SELECTION
TRANSFER
DATA DURING
CONVERSION
NO
APPLY
SYNC
(IF REQUIRED), SCLK, WRITE
TO CONTROL REGISTER SETTING NEXT
CHANNEL, CONVST BIT TO 1, READ
RESULT ON DOUT PIN FOR
CONVERSION JUST COMPLETED
WAIT FOR BUSY SIGNAL TO GO LOW
OR
WAIT FOR BUSY BIT = 0
YES
2
TRANSFER
DATA DURING
CONVERSION
Figure 35. Flowchart for Setting Up, Reading and Writing in Interface Mode 2
that no valid data is written to any of the registers. When using
the software conversion start and transferring data during con-
version, Note 1 must be obeyed.
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