
REV. B
–6–
AD7853/AD7853L
ABSOLUTE MAXIMUM RATINGS
1
(T
A
= +25
°
C unless otherwise noted)
AV
DD
to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
DV
DD
to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AV
DD
to DV
DD
. . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Analog Input Voltage to AGND . . . . –0.3 V to AV
DD
+ 0.3 V
Digital Input Voltage to DGND . . . . –0.3 V to DV
DD
+ 0.3 V
Digital Output Voltage to DGND . . . –0.3 V to DV
DD
+ 0.3 V
REF
IN
/REF
OUT
to AGND . . . . . . . . . –0.3 V to AV
DD
+ 0.3 V
Input Current to Any Pin Except Supplies
2
. . . . . . . .
±
10 mA
Operating Temperature Range
Commercial (A, B Versions) . . . . . . . . . . . –40
°
C to +85
°
C
Storage Temperature Range . . . . . . . . . . . –65
°
C to +150
°
C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150
°
C
Plastic DIP Package, Power Dissipation . . . . . . . . . . 450 mW
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 105
°
C/W
θ
JC
Thermal Impedance . . . . . . . . . . . . . . . . . . . . 34.7
°
C/W
Lead Temperature, (Soldering, 10 sec) . . . . . . . . . . +260
°
C
SOIC, SSOP Package, Power Dissipation . . . . . . . . . 450 mW
θ
JA
Thermal Impedance . . . 75
°
C/W (SOIC) 115
°
C/W (SSOP)
θ
JC
Thermal Impedance . . . . 25
°
C/W (SOIC) 35
°
C/W (SSOP)
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215
°
C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220
°
C
ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >3 kV
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Transient currents of up to 100 mA will not cause SCR latch-up.
ORDERING GUIDE
Linearity
Error
(LSB)
1
±
1
±
1/2
±
1
±
1
±
1
±
1/2
±
1
±
1
±
1
±
1
Power
Dissipation
(mW)
Package
Options
2
Model
AD7853AN
AD7853BN
AD7853LAN
3
AD7853LBN
3
AD7853AR
AD7853BR
AD7853LAR
3
AD7853LBR
3
AD7853ARS
AD7853LARS
3
EVAL-AD7853CB
4
EVAL-CONTROL BOARD
5
20
20
6.85
6.85
20
20
6.85
6.85
6.85
6.85
N-24
N-24
N-24
N-24
R-24
R-24
R-24
R-24
RS-24
RS-24
NOTES
1
Linearity error refers to the integral linearity error.
2
N = Plastic DIP; R = SOIC; RS = SSOP.
3
L signifies the low power version.
4
This can be used as a stand-alone evaluation board or in conjunction with the
EVAL-CONTROL BOARD for evaluation/demonstration purposes.
5
This board is a complete unit allowing a PC to control and communicate with
all Analog Devices, Inc. evaluation boards ending in the CB designators.
PIN CONFIGURATIONS
DIP, SOIC AND SSOP
CAL
SCLK
SM2
SLEEP
REF
IN
/REF
OUT
BUSY
AIN(+)
AV
DD
AGND
CREF1
CREF2
AIN(–)
CONVST
DV
DD
SYNC
1
2
3
7
24
23
22
21
20
19
18
17
16
15
14
13
8
9
10
11
12
4
5
6
CLKIN
DIN
DOUT
DGND
AMODE
POLARITY
SM1
NC
AGND
NC = NO CONNECT
TOP VIEW
(Not to Scale)
AD7853/53L