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參數資料
| 型號： | EVAL-AD7853CB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 3 V to 5 V Single Supply, 200 kSPS 12-Bit Sampling ADCs |
| 中文描述： | 3 V至5 V單電源，200 kSPS的12位采樣ADC |
| 文件頁數： | 28/34頁 |
| 文件大?。?/td> | 350K |
| 代理商： | EVAL-AD7853CB |
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REV. B
–28–
AD7853/AD7853L
Writing to the AD7853/AD7853L
For accessing the on-chip registers it is necessary to write to the
part. To enable Serial Interface Mode 1, the user must also
write to the part. Figure 41 through 43 outline flowcharts of
how to configure the AD7853/AD7853L for each of the differ-
ent serial interface modes. The continuous loops on all diagrams
indicate the sequence for more than one conversion. The options
of using a hardware (pulsing the
CONVST
pin) or software
(setting the CONVST bit to 1) conversion start, and reading/
writing during or after conversion are shown in Figures 41 and
42. If the
CONVST
pin is never used then it should be tied to
DV
DD
permanently. Where reference is made to the BUSY bit
equal to a Logic 0, to indicate the end of conversion, the user in
this case would poll the BUSY bit in the status register.
Interface Modes 2 and 3 Configuration
Figure 41 shows the flowchart for configuring the part in Inter-
face Modes 2 and 3. For these interface modes, the read and
write operations take place simultaneously via the serial port.
Writing all 0s ensures that no valid data is written to any of the
registers. When using the software conversion start and transfer-
ring data during conversion, Note must be obeyed.
SERIAL
INTERFACE
MODE
POWER-ON, APPLY CLKIN SIGNAL,
WAIT FOR AUTOMATIC CALIBRATION
NO
YES
START
WAIT FOR BUSY SIGNAL TO GO
LOW OR WAIT FOR BUSY BIT = 0
PULSE
CONVST
PIN
TRANSFER
DATA
DURING
CONVERSION
APPLY
SYNC
(IF REQUIRED), SCLK, READ
CURRENT CONVERSION RESULT ON DOUT PIN,
AND WRITE ALL 0s ON DIN PIN
WAIT FOR BUSY SIGNAL TO GO LOW
OR WAIT FOR BUSY BIT = 0
APPLY
SYNC
(IF REQUIRED), SCLK, WRITE TO CONTROL
REGISTER SETTING CONVST BIT TO 1, READ CURRENT
CONVERSION RESULT ON DOUT PIN
2, 3
INITIATE
CONVERSION
IN
SOFTWARE
WAIT APPROXIMATLY 200ns
AFTER
CONVST
RISING EDGE
APPLY
SYNC
(IF REQUIRED),
SCLK, READ PREVIOUS CONVERSION
RESULT ON DOUT PIN,
AND WRITE ALL 0s ON DIN PIN
NO
YES
TRANSFER
DATA DURING
CONVERSION
APPLY
SYNC
(IF REQUIRED), SCLK, WRITE TO CONTROL
REGISTER SETTING CONVST BIT TO 1, READ PREVIOUS
CONVERSION RESULT ON DOUT PIN (SEE NOTE)
YES
NO
NOTE:
WHEN USING THE SOFTWARE CONVERSION START AND TRANSFERRING
DATA DURING CONVERSION THE USER MUST ENSURE THE CONTROL
REGISTER WRITE OPERATION EXTENDS BEYOND THE FALLING EDGE OF
BUSY. THE FALLING EDGE OF BUSY RESETS THE CONVST BIT TO 0 AND
ONLY AFTER THIS TIME CAN IT BE REPROGRAMMED TO 1 TO START THE
NEXT CONVERSION.
Figure 41. Flowchart for Setting Up, Reading and Writing in Interface Modes 2 and 3
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相關代理商/技術參數 |
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| EVAL-AD7854CB | 制造商:Analog Devices 功能描述:EVALUATION CONTROL BOARD - Bulk |
| EVAL-AD7856CB | 制造商:AD 制造商全稱:Analog Devices 功能描述:5 V Single Supply, 8-Channel 14-Bit 285 kSPS Sampling ADC |
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| EVAL-AD7858CB4 | 制造商:AD 制造商全稱:Analog Devices 功能描述:3 V to 5 V Single Supply, 200 kSPS 8-Channel, 12-Bit Sampling ADC |
| EVAL-AD7859CB | 制造商:Analog Devices 功能描述:Evaluation Board For 3V To 5V, 12-Bit 200KSPS, Multi-Channel, Sampling ADC |
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