參數(shù)資料
型號(hào)： EVAL-AD7730LEB
廠商： Analog Devices, Inc.
英文描述： 10K RESISTOR 1/10 W
中文描述： 橋傳感器模數(shù)轉(zhuǎn)換器
文件頁(yè)數(shù)： 8/52頁(yè)
文件大?。?/td> 497K
代理商： EVAL-AD7730LEB
AD7730/AD7730L
–8–
REV. A
Pin
No.
Mnemonic
Function
3
MCLK OUT
When the master clock for the device is a crystal/resonator, the crystal/resonator is connected between MCLK IN
and MCLK OUT . If an external clock is applied to the MCLK IN, MCLK OUT provides an inverted clock sig-
nal. T his clock can be used to provide a clock source for external circuits and MCLK OUT is capable of driving
one CMOS load. If the user does not require it, MCLK OUT can be turned off with the CLK DIS bit of the Mode
Register. T his ensures that the part is not burning unnecessary power driving capacitance on the MCLK OUT pin.
Clock Polarity. Logic Input. T his determines the polarity of the serial clock. If the active edge for the proces-
sor is a high-to-low SCLK transition, this input should be low. In this mode, the AD7730 puts out data on the
DAT A OUT line in a read operation on a low-to-high transition of SCLK and clocks in data from the DAT A
IN line in a write operation on a high-to-low transition of SCLK . In applications with a noncontinuous serial
clock (such as most microcontroller applications), this means that the serial clock should idle low between
data transfers. If the active edge for the processor is a low-to-high SCLK transition, this input should be high.
In this mode, the AD7730 puts out data on the DAT A OUT line in a read operation on a high-to-low transi-
tion of SCLK and clocks in data from the DAT A IN line in a write operation on a low-to-high transition of
SCLK . In applications with a noncontinuous serial clock (such as most microcontroller applications), this
means that the serial clock should idle high between data transfers.
Logic Input that allows for synchronization of the digital filters and analog modulators when using a number
of AD7730s. While
SYNC
is low, the nodes of the digital filter, the filter control logic and the calibration
control logic are reset and the analog modulator is also held in its reset state.
SYNC
does not affect the digital
interface but does reset
RDY
to a high state if it is low. While
SYNC
is asserted, the Mode Bits may be set up
for a subsequent operation which will commence when the
SYNC
pin is deasserted.
Logic Input. Active low input that resets the control logic, interface logic, digital filter, analog modulator and
all on-chip registers of the part to power-on status. Effectively, everything on the part except for the clock
oscillator is reset when the
RESET
pin is exercised.
Analog Output. T his analog output is an internally-generated voltage used as an internal operating bias point.
T his output is not for use external to the AD7730 and it is recommended that the user does not connect any-
thing to this pin.
Ground reference point for analog circuitry.
Analog Positive Supply Voltage. T he AV
DD
to AGND differential is 5 V nominal.
Analog Input Channel 1. Positive input of the differential, programmable-gain primary analog input pair. T he
differential analog input ranges are 0 mV to +10 mV, 0 mV to +20 mV, 0 mV to +40 mV and 0 mV to +80 mV
in unipolar mode, and
±
10 mV,
±
20 mV,
±
40 mV and
±
80 mV in bipolar mode.
Analog Input Channel 1. Negative input of the differential, programmable gain primary analog input pair.
Analog Input Channel 2 or Digital Output 1. T his pin can be used either as part of a second analog input
channel or as a digital output bit as determined by the DEN bit of the Mode Register. When selected as an
analog input, it is the positive input of the differential, programmable-gain secondary analog input pair. T he
analog input ranges are 0 mV to +10 mV, 0 mV to +20 mV, 0 mV to +40 mV and 0 mV to +80 mV in unipo-
lar mode and
±
10 mV,
±
20 mV,
±
40 mV and
±
80 mV in bipolar mode. When selected as a digital output,
this output can programmed over the serial interface using bit D1 of the Mode Register.
Analog Input Channel 2 or Digital Output 0. T his pin can be used either as part of a second analog input channel
or as a digital output bit as determined by the DEN bit of the Mode Register. When selected as an analog input, it
is the negative input of the differential, programmable-gain secondary analog input pair. When selected as a digital
output, this output can programmed over the serial interface using bit D0 of the Mode Register.
Reference Input. Positive terminal of the differential reference input to the AD7730. REF IN(+) can lie
anywhere between AV
DD
and AGND. T he nominal reference voltage (the differential voltage between REF
IN(+) and REF IN(–)) should be +5 V when the HIREF bit of the Mode Register is 1 and +2.5 V when the
HIREF bit of the Mode Register is 0.
Reference Input. Negative terminal of the differential reference input to the AD7730. T he REF IN(–) poten-
tial can lie anywhere between AV
DD
and AGND.
Digital Output. Provides a signal that can be used to control the reversing of the bridge excitation in ac-
excited bridge applications. When ACX is high, the bridge excitation is taken as normal and when ACX is
low, the bridge excitation is reversed (chopped). If AC = 0 (ac mode turned off) or CHP = 0 (chop mode
turned off), the ACX output remains high.
Digital Output. Provides a signal that can be used to control the reversing of the bridge excitation in ac-
excited bridge applications. T his output is the complement of ACX . In ac mode, this means that it toggles in
anti-phase with ACX . If AC = 0 (ac mode turned off) or CHP = 0 (chop mode turned off), the
ACX
output
remains low. When toggling, it is guaranteed to be nonoverlapping with ACX . T he non-overlap interval, when
both ACX and
ACX
are low, is one master clock cycle.
4
POL
5
SYNC
6
RESET
7
V
BIAS
8
9
AGND
AV
DD
AIN1(+)
10
11
12
AIN1(–)
AIN2(+)/D1
13
AIN2(–)/D0
14
REF IN(+)
15
REF IN(–)
16
ACX
17
ACX
相關(guān)PDF資料
PDF描述
EVAL-AD7730EB Bridge Transducer ADC
EVAL-AD7731EB Low Noise, High Throughput 24-Bit Sigma-Delta ADC
EVAL-AD7751EB Energy Metering IC With On-Chip Fault Detection
EVAL-AD7755EB Energy Metering IC with Pulse Output
EVAL-AD7783EB Read-Only, Pin Configured 24-Bit ADC with Excitation Current Sources
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EVAL-AD7730LEBZ 功能描述:BOARD EVALUATION FOR AD7730 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:- 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標(biāo)準(zhǔn)）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件
EVAL-AD7731EB 制造商:Analog Devices 功能描述:EVALUATION BOARD I.C. - Bulk
EVAL-AD7731EBZ 功能描述:BOARD EVALUATION FOR AD7731 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:- 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標(biāo)準(zhǔn)）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件
EVAL-AD7732EB 制造商:Analog Devices 功能描述:2-CHANNEL, ??10 V INPUT RANGE, HIGH THROUGHPUT, 24-BIT ADC
EVAL-AD7732EBZ 功能描述:BOARD EVAL FOR AD7732 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:- 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標(biāo)準(zhǔn)）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*