參數(shù)資料
型號(hào): EVAL-AD7730LEB
廠商: Analog Devices, Inc.
英文描述: 10K RESISTOR 1/10 W
中文描述: 橋傳感器模數(shù)轉(zhuǎn)換器
文件頁數(shù): 44/52頁
文件大小: 497K
代理商: EVAL-AD7730LEB
LOW POWER
BRIDGE TRANSDUCER ADC
KEY FEATURES
Resolution of 110,000 Counts (Peak-to-Peak)
Power Consumption: 15 mW typ
Offset Drift: < 1 ppm/
8
C
Gain Drift: 3 ppm/
8
C
Line Frequency Rejection: >150 dB
Buffered Differential Inputs
Programmable Filter Cutoffs
Specified for Drift Over Time
Operates with Reference Voltages of 1 V to 5 V
ADDITIONAL FEATURES
Two-Channel Programmable Gain Front End
On-Chip DAC for Offset/TARE Removal
FASTStep Mode
AC or DC Excitation
Single Supply Operation
APPLICATIONS
Portable Weigh Scales
FUNCT IONAL BLOCK DIAGRAM
*
Protected by U.S. Patent No: 5, 134, 401. Other Patent Applications Filed.
a
APPENDIX–AD7730L*
–44–
GE NE RAL DE SCRIPT ION
T he AD7730L is a complete low power analog front-end for
weigh-scale and pressure measurement applications. T he device
accepts low level signals directly from a transducer and outputs
a serial digital word. T he input signal is applied to a proprietary
programmable gain front end based around an analog modula-
tor. T he modulator output is processed by a low pass program-
mable digital filter, allowing adjustment of filter cutoff, output
rate and settling-time.
T he part features two buffered differential programmable gain
analog inputs as well as a differential reference input. T he part
operates from a single +5 V supply and typically consumes less
than 3 mA. It accepts four unipolar analog input ranges: 0 mV
to +10 mV, +20 mV, +40 mV and +80 mV and four bipolar
ranges
±
10 mV,
±
20 mV,
±
40 mV and
±
80 mV. T he peak-to-
peak resolution achievable directly from the part is 1 in 110,000
counts. An on-chip 6-bit DAC allows the removal of T ARE
voltages. Clock signals for synchronizing ac excitation of the
bridge are also provided.
T he serial interface on the part can be configured for three-wire
operation and is compatible with microcontrollers and digital
signal processors. T he AD7730L contains self-calibration and
system calibration options and features an offset drift of less
than 5 nV/
°
C and a gain drift of less than 3 ppm/
°
C.
T he part is available in a 24-lead SOIC and 24-lead T SSOP
package.
SIGMA-
DELTA
MODULATOR
AD7730L
6-BIT
DAC
SERIAL INTERFACE
AND CONTROL LOGIC
REGISTER BANK
CLOCK
GENERATION
PROGRAMMABLE
DIGITAL
FILTER
SIGMA-DELTA A/D CONVERTER
BUFFER
PGA
100nA
AGND
100nA
AV
DD
VBIAS
AIN1(+)
AIN1(–)
AIN2(+)/D1
AIN2(–)/D0
ACX
ACX
STANDBY
SYNC
MCLK IN
MCLK OUT
SCLK
CS
DIN
DOUT
RESET
RDY
POL
DGND
AGND
AV
DD
DV
DD
REF IN(–) REF IN(+)
MUX
REFERENCE DETECT
AC
EXCITATION
CLOCK
+
REV. A
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