參數(shù)資料
型號： EVAL-AD7730EB
廠商： Analog Devices, Inc.
英文描述： Bridge Transducer ADC
中文描述： 橋傳感器模數(shù)轉(zhuǎn)換器
文件頁數(shù)： 7/52頁
文件大小： 497K
代理商： EVAL-AD7730EB
AD7730/AD7730L
REV. A
–7–
Figure 3. Signal Processing Chain
PIN CONFIGURAT ION
PIN FUNCT ION DE SCRIPT IONS
Pin
No.
Mnemonic
Function
1
SCLK
Serial Clock. Schmitt-T riggered Logic Input. An external serial clock is applied to this input to transfer serial
data to or from the AD7730. T his serial clock can be a continuous clock with all data transmitted in a con-
tinuous train of pulses. Alternatively, it can be a noncontinuous clock with the information being transmitted
to or from the AD7730 in smaller batches of data.
Master Clock signal for the device. T his can be provided in the form of a crystal/resonator or external clock. A
crystal/resonator can be tied across the MCLK IN and MCLK OUT pins. Alternatively, the MCLK IN pin
can be driven with a CMOS-compatible clock and MCLK OUT left unconnected. T he AD7730 is specified
with a clock input frequency of 4.9152 MHz while the AD7730L is specified with a clock input frequency of
2.4576 MHz.
2
MCLK IN
SCLK
MCLK IN
DGND
DV
DD
SYNC
V
BIAS
RDY
CS
MCLK OUT
POL
DIN
DOUT
AGND
AV
DD
ACX
AIN1(+)
STANDBY
14
1
2
24
23
5
6
7
20
19
18
3
4
22
21
8
17
9
16
10
15
11
TOP VIEW
(Not to Scale)
12
13
AD7730
RESET
REF IN(–)
REF IN(+)
AIN1(–)
AIN2(+)/D1
AIN2(–)/D0
ACX
PGA +
SIGMA-DELTA
MODULATOR
SINC
3
FILTER
CHOP
22-TAP
FIR FILTER
FASTSTEP
FILTER
CHOP
INPUT CHOPPING
THE ANALOG INPUT TO THE PART CAN BE
CHOPPED. IN CHOPPING MODE, WITH
AC EXCITATION DISABLED, THE INPUT
CHOPPING IS INTERNALTO THE DEVICE. IN
CHOPPING MODE, WITH AC EXCITATION
ENABLED, THE CHOPPING IS ASSUMED
TO BE PERFORMED EXTERNAL TO THE PART
AND NO INTERNAL INPUT CHOPPING IS
PERFORMED. THE INPUT CHOPPING CAN
BE DISABLED, IF DESIRED.
SEE PAGE 26
ANALOG
INPUT
DIGITAL
OUTPUT
SINC
3
FILTER
THE FIRST STAGE OF THE DIGITAL FILTERING
FILTER. THE
OSKIP MODE, THE SINC
3
ONLY FILTERING PERFOR FILTER IS THE
SEE PAGE 26
BUFFER
SKIP MODE
SIN SKIP MODE, THERE IS NO SECOND
SINC
FILTER IS THE ONLY FILTERING
PERFORMED ON THE PART.
SEE PAGE 29
SKIP
OUTPUT
SCALING
22-TAP FIR FILTER
SEON THE PART IS A FIXED 22-TAP FIR
BYPASSED. WHEN FASTSTEP
DETEIS PERFORMED BY THE FILTER
UNTIL HAS FULLY SETTLED.
SEE PAGE 27
OUTPUT SCALING
THE OUTPUT WORD FROM THE DIGITAL
FILTER IS SCALED BY THE CALIBRATION
COEFFICIENTS BEFORE BEING PROVIDED
AS THE CONVERSION RESULT.
SEE PAGE 29
FASTSTEP FILTER
WHEN FASTSTEP MODE IS ENABLED
HAS BEEN DETECTED, THE SECOND
STAFASTSTEP FILTER UNTIL THE FIR
FILTER HAS FULLY SETTLED.
SEE PAGE 29
OUTPUT CHOPPING
THE OUTPUT OF THE FIRST STAGE
OF FILTERING ON THE PART CAN
BE CHOPPED. IN CHOPPING MODE,
REGARDLESS OF WHETHER AC
EXCITATION IS ENABLED OR DISABLED,
THE OUTPUT CHOPPING IS
PERFORMED. THE CHOPPING CAN
BE DISABLED, IF DESIRED.
SEE PAGE 26
PGA + SIGMA-DELTA MODULATOR
THOF THE PART IS INCORPORATED
ATHE MODULATOR PROVIDES A HIGH-
FRETO THE DIGITAL FILTER.
SEE PAGE 26
BUFFER
THE SAMPLING CAPACITOR OF THE
ISCHARGING CURRENTS FROM THE
ANALOG INPUT PINS.
SEE PAGE 24
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EVAL-AD7730LEB 制造商:Analog Devices 功能描述:EVALUATION BOARD I.C. - Bulk
EVAL-AD7730LEBZ 功能描述:BOARD EVALUATION FOR AD7730 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:- 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標(biāo)準(zhǔn)）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件
EVAL-AD7731EB 制造商:Analog Devices 功能描述:EVALUATION BOARD I.C. - Bulk
EVAL-AD7731EBZ 功能描述:BOARD EVALUATION FOR AD7731 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:- 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標(biāo)準(zhǔn)）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件
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