- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄362802 > EVAL-AD7730EB (Analog Devices, Inc.) Bridge Transducer ADC PDF資料下載
參數(shù)資料
| 型號： | EVAL-AD7730EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Bridge Transducer ADC |
| 中文描述： | 橋傳感器模數(shù)轉換器 |
| 文件頁數(shù)： | 22/52頁 |
| 文件大?。?/td> | 497K |
| 代理商： | EVAL-AD7730EB |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁當前第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁
AD7730/AD7730L
–22–
REV. A
CALIBRAT ION OPE RAT ION SUMMARY
T he AD7730 contains a number of calibration options as outlined previously. T able X VII summarizes the calibration types, the
operations involved and the duration of the operations. T here are two methods of determining the end of calibration. T he first is to
monitor the hardware
RDY
pin using either interrupt-driven or polling routines. T he second method is to do a software poll of the
RDY
bit in the Status Register. T his can be achieved by setting up the part for continuous reads of the Status Register once a calibra-
tion has been initiated. T he
RDY
pin and
RDY
bit go high on initiating a calibration and return low at the end of the calibration
routine. At this time, the MD2, MD1, MD0 bits of the Mode Register have returned to 0, 0, 0. T he FAST and SK IP bits are treated
as 0 for the calibration sequence so the full filter is always used for the calibration routines. See Calibration section for full detail.
T able X VII. Calibration Operations
MD2, MD1,
MD0
Duration to
RDY
Low (CHP = 1)
Duration to
RDY
Low (CHP = 0)
Calibration T ype
Calibration Sequence
Internal Zero-Scale
1, 0, 0
22
×
1/Output Rate
24
×
1/Output Rate
Calibration on internal shorted input with PGA set for
selected input range. T he ac bit is ignored for this calibra-
tion sequence. T he sequence is performed with dc excitation.
T he Offset Calibration Register for the selected channel is
updated at the end of this calibration sequence. For full self-
calibration, this calibration should be preceded by an Internal
Full-Scale calibration. For applications which require an
Internal Zero-Scale and System Full-Scale calibration, this
Internal Zero-Scale calibration should be performed first.
Calibration on internally-generated input full-scale with
PGA set for selected input range. T he ac bit is ignored for
this calibration sequence. T he sequence is performed with
dc excitation. T he Gain Calibration Register for the
selected channel is updated at the end of this calibration
sequence. It is recommended that internal full-scale
calibrations are performed on the 80 mV range, regardless
of the subsequent operating range, to optimize the post-
calibration gain error. T his calibration should be followed
by either an Internal Zero-Scale or System Zero-Scale
calibration. T his zero-scale calibration should be
performed at the operating input range.
Calibration on externally applied input voltage with PGA
set for selected input range. T he input applied is assumed
to be the zero scale of the system. If ac = 1, the system
continues to use ac excitation for the duration of the
calibration. For full system calibration, this System Zero-
Scale calibration should be performed first. For applications
which require a System Zero-Scale and Internal Full-Scale
calibration, this calibration should be preceded by the
Internal Full-Scale calibration. T he Offset Calibration
Register for the selected channel is updated at the end of
this calibration sequence.
Calibration on externally-applied input voltage with PGA
set for selected input range. T he input applied is assumed
to be the full-scale of the system. If ac = 1, the system
continues to use ac excitation for the duration of the
calibration. T his calibration should be preceded by a
System Zero-Scale or Internal Zero-Scale calibration. T he
Gain Calibration Register for the selected channel is
updated at the end of this calibration sequence.
Internal Full-Scale
1, 0, 1
44
×
1/Output Rate
48
×
1/Output Rate
System Zero-Scale
1, 1, 0
22
×
1/Output Rate
24
×
1/Output Rate
System Full-Scale
1, 1, 1
22
×
1/Output Rate
24
×
1/Output Rate
相關PDF資料 |
PDF描述 |
|---|---|
| EVAL-AD7731EB | Low Noise, High Throughput 24-Bit Sigma-Delta ADC |
| EVAL-AD7751EB | Energy Metering IC With On-Chip Fault Detection |
| EVAL-AD7755EB | Energy Metering IC with Pulse Output |
| EVAL-AD7783EB | Read-Only, Pin Configured 24-Bit ADC with Excitation Current Sources |
| EVAL-AD7843CB | Touch Screen Digitizer |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| EVAL-AD7730EBZ | 功能描述:BOARD EVAL FOR AD7730 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 模數(shù)轉換器 (ADC) 系列:- 產(chǎn)品培訓模塊:Obsolescence Mitigation Program 標準包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標準）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
| EVAL-AD7730LEB | 制造商:Analog Devices 功能描述:EVALUATION BOARD I.C. - Bulk |
| EVAL-AD7730LEBZ | 功能描述:BOARD EVALUATION FOR AD7730 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 模數(shù)轉換器 (ADC) 系列:- 產(chǎn)品培訓模塊:Obsolescence Mitigation Program 標準包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標準）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
| EVAL-AD7731EB | 制造商:Analog Devices 功能描述:EVALUATION BOARD I.C. - Bulk |
| EVAL-AD7731EBZ | 功能描述:BOARD EVALUATION FOR AD7731 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 模數(shù)轉換器 (ADC) 系列:- 產(chǎn)品培訓模塊:Obsolescence Mitigation Program 標準包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標準）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
發(fā)布緊急采購，3分鐘左右您將得到回復。