參數(shù)資料
型號： EVAL-AD7711EB
廠商： Analog Devices, Inc.
英文描述： CERAMIC CHIP CAPACITOR
中文描述： LC2MOS信號調(diào)理型ADC RTD激勵電流
文件頁數(shù)： 3/28頁
文件大?。?/td> 242K
代理商： EVAL-AD7711EB
Parameter
V
BIAS
INPUT
12
A, S Versions
1
Units
Conditions/Comments
AV
– 0.85
×
V
REF
or AV
DD
– 3.5
See V
Input Section
Whichever Is Smaller; +5 V/–5 V or +10 V/0 V
Nominal AV
DD
/V
SS
Whichever Is Smaller; +5 V/0 V Nominal AV
DD
/V
SS
See V
BIAS
Input Section
Whichever Is Greater; +5 V/–5 V or +10 V/0 V
Nominal AV
DD
/V
SS
Whichever Is Greater; +5 V/0 V Nominal AV
DD
/V
SS
Increasing with Gain
V max
or AV
DD
– 2.1
V
SS
+ 0.85
×
V
REF
or V
SS
+ 3
V max
V min
or V
+ 2.1
65 to 85
V min
dB typ
V
BIAS
Rejection
LOGIC INPUTS
Input Current
All Inputs except MCLK IN
V
INL
, Input Low Voltage
V
INH
, Input High Voltage
MCLK IN Only
V
INL
, Input Low Voltage
V
INH
, Input High Voltage
LOGIC OUTPUTS
V
OL
, Output Low Voltage
V
, Output High Voltage
Floating State Leakage Current
Floating State Output Capacitance
13
TRANSDUCER BURNOUT
Current
Initial Tolerance @ +25
°
C
Drift
RTD EXCITATION CURRENTS (RTD1, RTD2)
Output Current
Initial Tolerance @ +25
°
C
Drift
Initial Matching @ +25
°
C
Drift Matching
Line Regulation (AV
DD
)
Load Regulation
Output Compliance
SYSTEM CALIBRATION
Positive Full-Scale Calibration Limit
14
Negative Full-Scale Calibration Limit
14
Offset Calibration Limit
15
Input Span
15
±
10
μ
A max
0.8
2.0
V max
V min
0.8
3.5
V max
V min
0.4
4.0
±
10
9
V max
V min
μ
A max
pF typ
I
SINK
= 1.6 mA
I
SOURCE
= 100
μ
A
4.5
±
10
0.1
μ
A nom
% typ
%/
°
C typ
200
±
20
20
±
1
3
200
200
AV
DD
– 2
μ
A nom
% max
ppm/
°
C typ
% max
ppm/
°
C typ
nA/V max
nA/V max
V max
Matching Between RTD1 and RTD2 Currents
Matching Between RTD1 and RTD2 Current Drift
AV
DD
= +5 V
(1.05
×
V
REF
)/GAIN
–(1.05
×
V
REF
)/GAIN
–(1.05
×
V
REF
)/GAIN
0.8
×
V
REF
/GAIN
(2.1
×
V
REF
)/GAIN
V max
V max
V max
V min
V max
GAIN Is the Selected PGA Gain (Between 1 and 128)
GAIN Is the Selected PGA Gain (Between 1 and 128)
GAIN Is the Selected PGA Gain (Between 1 and 128)
GAIN Is the Selected PGA Gain (Between 1 and 128)
GAIN Is the Selected PGA Gain (Between 1 and 128)
NOTES
12
The AD7711 is tested with the following V
voltages. With AV
DD
= +5 V and V
SS
= 0 V, V
BIAS
= +2.5 V; with AV
DD
= +10 V and V
SS
= 0 V, V
BIAS
= +5 V and
with AV
= +5 V and V
= –5 V, V
= 0 V.
13
Guaranteed by design, not production tested.
14
After calibration, if the analog input exceeds positive full scale, the converter will output all 1s. If the analog input is less than negative full scale, then the device will
output all 0s.
15
These calibration and span limits apply provided the absolute voltage on the analog inputs does not exceed AV
DD
+ 30 mV or go more negative than V
SS
– 30 mV.
The offset calibration limit applies to both the unipolar zero point and the bipolar zero point.
–3–
REV. F
AD7711
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