參數(shù)資料
型號(hào)： EVAL-AD7711EB
廠商： Analog Devices, Inc.
英文描述： CERAMIC CHIP CAPACITOR
中文描述： LC2MOS信號(hào)調(diào)理型ADC RTD激勵(lì)電流
文件頁(yè)數(shù)： 27/28頁(yè)
文件大?。?/td> 242K
代理商： EVAL-AD7711EB
2
AD7711
–27–
REV. F
APPLICATIONS
Four-Wire RTD Configurations
Figure 20 shows a four-wire RTD application where the RTD
transducer is interfaced directly to the AD7711. In the four-wire
configuration, there are no errors associated with lead resis-
tances as no current flows in the measurement leads connected
to AIN1(+) and AIN1(–). One of the RTD current sources is
used to provide the excitation current for the RTD. A common
nominal resistance value for the RTD is 100
and, therefore,
the RTD will generate a 20 mV signal which can be handled
directly by the analog input of the AD7711. In the circuit
shown, the second RTD excitation current is used to generate
the reference voltage for the AD7711. This reference voltage is
developed across R
REF
and applied to the differential reference
inputs. For the nominal reference voltage of +2.5 V, R
REF
is
12.5 k
. This scheme ensures that the analog input voltage span
remains ratiometric to the reference voltage. Any errors in the
analog input voltage due to the temperature drift of the RTD
current source is compensated for by the variation in the refer-
ence voltage. The typical matching between the two RTD cur-
rent sources is less than 3 ppm/
°
C.
INTERNAL
CIRCUITRY
200
m
A
200
m
A
PGA
AD7711
A = 1–128
RTD2
REF IN(+)
REF IN(–)
RTD1
AIN1(+)
AIN1(–)
AGND
R
REF
RTD
+5V
AV
DD
DV
DD
V
SS
DGND
Figure 20. Four-Wire RTD Application with the AD7711
Three-Wire RTD Configurations
One possible three-wire configuration using the AD7711 is
outlined in Figure 21. In the three-wire configuration, the lead
resistances will result in errors if only one current source is used
as the 200
μ
A will flow through R
L1
developing a voltage error
between AIN1(+) and AIN1(–). In the scheme outlined below,
the second RTD current source is used to compensate for the
error introduced by the 200
μ
A flowing through R
L1
. The sec-
ond RTD current flows through R
L2
. Assuming R
L1
and R
L2
are
equal (the leads would normally be of the same material and of
equal length) and RTD1 and RTD2 match, then the error volt-
age across R
L2
equals the error voltage across R
L1
and no error
voltage is developed between AIN1(+) and AIN1(–). Twice the
voltage is developed across R
L3
but since this is a common-
mode voltage it will not introduce any errors. The circuit of
Figure 21 shows the reference voltage for the AD7711 derived
from the parts own internal reference.
V
SS
DGND
ANALOG +5V SUPPLY
AV
DD
DV
DD
REF IN(+)
REF OUT
2.5V
REFERENCE
REF IN(–)
200
m
A
RTD1
PGA
A = 1–128
AIN1(+)
AIN1(–)
INTERNAL
CIRCUITRY
200
m
A
AD7711
AGND
R
L1
R
L2
R
L3
RTD2
RTD
Figure 21. Three-Wire RTD Application with the AD7711
The circuit of Figure 22 shows an alternate three-wire configu-
ration. In this case, the circuit has the same benefits in terms of
eliminating lead resistance errors as outlined in Figure 21, but it
has the additional benefit that the reference voltage is derived
from one of the current sources. This gives all the benefits of
eliminating RTD tempco errors as outlined in Figure 20. The
voltage on either RTD input can go to within 2 V of the AV
DD
supply. The circuit is shown for a +2.5 V reference.
V
SS
DGND
AV
DD
DV
DD
REF IN(+)
200
m
A
RTD1
PGA
A = 1–128
AIN1(+)
AIN1(–)
INTERNAL
CIRCUITRY
200
m
A
AD7711
AGND
R
L1
R
L2
R
L3
RTD2
REF IN(–)
12.5k
V
RTD
Figure 22. Alternate Three-Wire Configuration
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