TA = 25掳C, f
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� EVAL-AD7451CBZ
寤犲晢锛� Analog Devices Inc
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 3/25闋�(y猫)
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� BOARD EVAL FOR AD7451
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 1
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鍦ㄤ互涓嬫浠朵笅鐨勯浕婧愶紙妯�(bi膩o)婧�(zh菙n)锛夛細 9.25mW @ 1MSPS锛�5V
宸ヤ綔婧害锛� -40°C ~ 85°C
宸茬敤 IC / 闆朵欢锛� AD7451
宸蹭緵鐗╁搧锛� 鏉�
AD7441/AD7451
Rev. D | Page 10 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25掳C, fS = 1 MSPS, fSCLK = 18 MHz, VDD = 2.7 V to 5.25 V, VREF = 2.5 V, unless otherwise noted.
75
55
60
65
70
10
100
1000
FREQUENCY (kHz)
S
INAD
(
d
B
)
VDD = 5.25V
VDD = 4.75V
VDD = 3.6V
VDD = 2.7V
03
15
3
-00
7
Figure 7. SINAD vs. Analog Input Frequency for the AD7451 for
Various Supply Voltages
0
鈥�120
鈥�80
鈥�100
鈥�60
鈥�40
鈥�20
0
100
200
300
400
500
600
700
800
900 1000
SUPPLY RIPPLE FREQUENCY (kHz)
P
S
RR
(
d
B)
100mV p-p SINE WAVE ON VDD
NO DECOUPLING ON VDD
VDD = 3V
VDD = 5V
03
15
3
-00
8
Figure 8. PSRR vs. Supply Ripple Frequency Without Supply Decoupling
FREQUENCY (kHz)
S
N
R
(
d
B)
0
100
200
鈥�100
鈥�140
500
鈥�20
0
鈥�120
鈥�40
鈥�60
鈥�80
8192 POINT FFT
fSAMPLE = 1MSPS
fIN = 100kSPS
SINAD = 71dB
THD = 鈥�82dB
SFDR = 鈥�83dB
300
400
0
315
3-
0
09
Figure 9. AD7451 Dynamic Performance for VDD = 5 V
D
NL
E
R
RO
R
(
L
S
B
)
CODE
0.4
0
1024
2048
3072
0.2
0
鈥�0.2
鈥�0.4
鈥�1.0
4096
0.6
0.8
1.0
鈥�0.6
鈥�0.8
03
15
3-
0
10
Figure 10. Typical DNL for the AD7451 for VDD = 5 V
INL
E
RRO
R
(
L
S
B)
CODE
0.4
0
1024
2048
3072
0.2
0
鈥�0.2
鈥�0.4
鈥�1.0
4096
0.6
0.8
1.0
鈥�0.6
鈥�0.8
03
15
3-
0
11
Figure 11. Typical INL for the AD7451 for VDD = 5 V
CO
UNT
S
CODES
0
2046
2047
2048
2049
2050
2051
27 CODES
24 CODES
1000
2000
3000
4000
5000
6000
7000
8000
9000
10000
9949
CODES
03
15
3-
0
12
Figure 12. Histogram of 10,000 Conversions of a DC Input for the AD7451
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STD02W-T WIRE & CABLE MARKERS
STD09W-J WIRE & CABLE MARKERS
HKQ0603S0N8C-T INDUCTOR HI FREQ 0.8NH 0201
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EVAL-AD7949EDZ BOARD EVAL AD7949
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鍙冩暩(sh霉)鎻忚堪
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