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參數(shù)資料
| 型號(hào)： | EVAL-AD7451CBZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 21/25頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD7451 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 1M |
| 數(shù)據(jù)接口： | SPI?、QSPI?、MICROWIRE? 和 DSP |
| 輸入范圍： | ±VREF |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | 9.25mW @ 1MSPS，5V |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7451 |
| 已供物品： | 板 |
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AD7441/AD7451
Rev. D | Page 4 of 24
Parameter
Test Conditions/Comments
A Version
B Version
Unit
CONVERSION RATE
Conversion Time
888 ns with an 18 MHz SCLK
16
SCLK cycles
Track-and-Hold Acquisition Time1
Sine wave input
250
ns max
Full-scale step input
290
ns max
Throughput Rate
1
MSPS max
POWER REQUIREMENTS
VDD
2.7/5.25
V min/max
Normal Mode (Static)
SCLK on or off
0.5
mA typ
Normal Mode (Operational)
VDD = 4.75 V to 5.25 V
1.95
mA max
VDD = 2.7 V to 3.6 V
1.45
mA max
Full Power-Down Mode
SCLK on or off
1
μA max
Power Dissipation
Normal Mode (Operational)
9.25
mW max
4
mW max
Full Power-Down
VDD = 5 V; SCLK on or off
5
μW max
VDD = 3 V; SCLK on or off
3
μW max
1 See Terminology section.
2 Analog inputs with slew rates exceeding 27 V/μs (full-scale input sine wave > 3.5 MHz) within the acquisition time can cause the converter to return an incorrect result.
3 A small dc input is applied to VIN– to provide a pseudo ground for VIN+.
4 The AD7451 is functional with a reference input in the range of 100 mV to VDD.
5 Guaranteed by characterization.
6 See the Power vs. Throughput Rate section.
7 Measured with a full-scale dc input.
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| EVAL-AD7451CBZ3 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Pseudo Differential Input, 1 MSPS, 10-/12-Bit ADCs in an 8-Lead SOT-23 |
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