Having fSCLK = 5" />
參數(shù)資料
型號(hào): EVAL-AD7451CBZ
廠商: Analog Devices Inc
文件頁數(shù): 10/25頁
文件大?。?/td> 0K
描述: BOARD EVAL FOR AD7451
標(biāo)準(zhǔn)包裝: 1
ADC 的數(shù)量: 1
位數(shù): 12
采樣率(每秒): 1M
數(shù)據(jù)接口: SPI?、QSPI?、MICROWIRE? 和 DSP
輸入范圍: ±VREF
在以下條件下的電源(標(biāo)準(zhǔn)): 9.25mW @ 1MSPS,5V
工作溫度: -40°C ~ 85°C
已用 IC / 零件: AD7451
已供物品:
AD7441/AD7451
Rev. D | Page 17 of 24
Timing Example 2
Timing Example 1
Having fSCLK = 5 MHz and a throughput rate of 315 kSPS gives a
cycle time of
Having fSCLK = 18 MHz and a throughput rate of 1 MSPS gives a
cycle time of
1/Throughput = 1/315,000 = 3.174 μs
1/Throughput = 1/1,000,000 = 1 μs
A cycle consists of
t2 + 12.5 (1/fSCLK) + tACQUISITION = 3.174 μs
t2 + 12.5 (1/fSCLK) + tACQUISITION = 1 μs
Therefore, if t2 is 10 ns, then
Therefore, if t2 = 10 ns, then
10 ns + 12.5 (1/5 MHz) + tACQUISITION = 3.174 μs
tACQUISITION = 664 ns
10 ns + 12.5 (1/18 MHz) + tACQUISITION = 1 μs
tACQUISITION = 296 ns
This 664 ns satisfies the requirement of 290 ns for tACQUISITION.
This 296 ns satisfies the requirement of 290 ns for tACQUISITION.
From Figure 28, tACQUISITION comprises
From Figure 28, tACQUISITION comprises
2.5 (1/fSCLK) + t8 = tQUIET
where t8 = 35 ns. This allows a value of 129 ns for tQUIET,
satisfying the minimum requirement of 60 ns.
where t8 = 35 ns. This allows a value of 122 ns for tQUIET,
satisfying the minimum requirement of 60 ns.
As in this example and with other slower clock values, the signal
can already be acquired before the conversion is complete, but it
is still necessary to leave 60 ns minimum tQUIET between conver-
sions. In Example 2, the signal is fully acquired at approximately
Point C in Figure 28.
t2
t8
t6
t5
tCONVERT
CS
SCLK
12
3
4
5
13
14
15
16
12.5(1/
fSCLK)
tACQUISITION
1/THROUGHPUT
tQUIET
10ns
B
C
03
15
3-
02
8
Figure 28. Serial Interface Timing Example
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