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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | EVAL-AD7366SDZ |
| 寤犲晢锛� | Analog Devices Inc |
| 鏂囦欢闋�(y猫)鏁�(sh霉)锛� | 28/29闋�(y猫) |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | BOARD EVAL FOR AD7366 |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 1 |
| 绯诲垪锛� | iCMOS® |
| ADC 鐨勬暩(sh霉)閲忥細 | 2 |
| 浣嶆暩(sh霉)锛� | 12 |
| 閲囨ǎ鐜囷紙姣忕锛夛細 | 1M |
| 鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� | 涓茶 |
| 杓稿叆鑼冨湇锛� | ±10 V |
| 鍦ㄤ互涓嬫浠朵笅鐨勯浕婧愶紙妯�(bi膩o)婧�(zh菙n)锛夛細 | 70mW @ 1MSPS |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 宸茬敤 IC / 闆朵欢锛� | AD7366 |
| 宸蹭緵鐗╁搧锛� | 鏉� |
绗�1闋�(y猫)绗�2闋�(y猫)绗�3闋�(y猫)绗�4闋�(y猫)绗�5闋�(y猫)绗�6闋�(y猫)绗�7闋�(y猫)绗�8闋�(y猫)绗�9闋�(y猫)绗�10闋�(y猫)绗�11闋�(y猫)绗�12闋�(y猫)绗�13闋�(y猫)绗�14闋�(y猫)绗�15闋�(y猫)绗�16闋�(y猫)绗�17闋�(y猫)绗�18闋�(y猫)绗�19闋�(y猫)绗�20闋�(y猫)绗�21闋�(y猫)绗�22闋�(y猫)绗�23闋�(y猫)绗�24闋�(y猫)绗�25闋�(y猫)绗�26闋�(y猫)绗�27闋�(y猫)鐣�(d膩ng)鍓嶇28闋�(y猫)绗�29闋�(y猫)
AD7366/AD7367
Rev. D | Page 7 of 28
TIMING SPECIFICATIONS
AVCC = DVCC = 4.75 V to 5.25 V, VDD = 11.5 V to 16.5 V, VSS = 16.5 V to 11.5 V, VDRIVE = 2.7 V to 5.25 V, TA = 40掳C to +85掳C,
unless otherwise noted.1
Table 4.
Parameter
Limit at T
MIN, TMAX
Unit
Test Conditions/Comments
2.7 V 鈮� V
DRIVE < 4.75 V
4.75 V 鈮� V
DRIVE 鈮� 5.25 V
t
CONVERT
Conversion time, internal clock; CNVST falling edge to
BUSY falling edge
680
ns max
AD7367
610
ns max
AD7366
f
SCLK
10
kHz min
Frequency of serial read clock
35
48
MHz max
t
QUIET
30
ns min
Minimum quiet time required between the end of serial
read and the start of the next conversion
t
1
10
ns min
Minimum CNVST low pulse
t
2
40
ns min
CNVST falling edge to BUSY rising edge
t
3
0
ns min
BUSY falling edge to MSB, valid when CS is low for t4 prior
to BUSY going low
t
4
10
ns max
Delay from CS falling edge until Pin 1 (DOUTA) and Pin 23
(D
OUTB) are three-state disabled
20
14
ns max
Data access time after SCLK falling edge
t
6
7
ns min
SCLK to data valid hold time
t
7
0.3 脳 t
SCLK
0.3 脳 t
SCLK
ns min
SCLK low pulse width
t
8
0.3 脳 t
SCLK
0.3 脳 t
SCLK
ns min
SCLK high pulse width
t
9
10
ns max
CS rising edge to DOUTA, DOUTB, high impedance
t
POWER-UP
70
s max
Power-up time from shutdown mode; time required
between CNVST rising edge and CNVST falling edge
1 Sample tested during initial release to ensure compliance. All input signals are specified with t
R = tF = 5 ns (10% to 90% of VDRIVE) and timed from a voltage level of 1.6 V.
All timing specifications are with a 25 pF load capacitance. With a load capacitance greater than 25 pF, a digital buffer or latch must be used. See the Terminology
section, Figure 25, and Figure 26.
2 The time required for the output to cross is 0.4 V or 2.4 V.
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
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| ESC06DRTH-S734 | CONN EDGECARD 12POS DIP .100 SLD |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| EVAL-AD7367CBZ | 鍒堕€犲晢:AD 鍒堕€犲晢鍏ㄧū:Analog Devices 鍔熻兘鎻忚堪:True Bipolar Input, Dual 1 銉瑂, 12-/14-Bit, 2-Channel SAR ADCs |
| EVAL-AD7367SDZ | 鍔熻兘鎻忚堪:鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻� IC 闁嬬櫦(f膩)宸ュ叿 EVALUATION CONTROL BOARD I.C. RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鐢�(ch菐n)鍝�:Demonstration Kits 椤炲瀷:ADC 宸ュ叿鐢ㄤ簬瑭�(p铆ng)浼�:ADS130E08 鎺ュ彛椤炲瀷:SPI 宸ヤ綔闆绘簮闆诲:- 6 V to + 6 V |
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| EVAL-AD7400AEBZ | 鍒堕€犲晢:Analog Devices 鍔熻兘鎻忚堪:EVALUATION BOARD I.C. - Bulk |
| EVAL-AD7400AEDZ | 鍔熻兘鎻忚堪:BOARD EVAL AD7400A RoHS:鏄� 椤炲垾:绶ㄧ▼鍣紝闁嬬櫦(f膩)绯荤当(t菕ng) >> 瑭�(p铆ng)浼版澘 - 妯℃暩(sh霉)杞�(zhu菐n)鎻涘櫒 (ADC) 绯诲垪:iCoupler® 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Obsolescence Mitigation Program 妯�(bi膩o)婧�(zh菙n)鍖呰:1 绯诲垪:- ADC 鐨勬暩(sh霉)閲�:1 浣嶆暩(sh霉):12 閲囨ǎ鐜囷紙姣忕锛�:94.4k 鏁�(sh霉)鎿�(j霉)鎺ュ彛:USB 杓稿叆鑼冨湇:±VREF/2 鍦ㄤ互涓嬫浠朵笅鐨勯浕婧愶紙妯�(bi膩o)婧�(zh菙n)锛�:- 宸ヤ綔婧害:-40°C ~ 85°C 宸茬敤 IC / 闆朵欢:MAX11645 宸蹭緵鐗╁搧:鏉�锛岃粺浠� |
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