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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | EVAL-AD7366SDZ |
| 寤犲晢锛� | Analog Devices Inc |
| 鏂囦欢闋佹暩(sh霉)锛� | 2/29闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | BOARD EVAL FOR AD7366 |
| 妯欐簴鍖呰锛� | 1 |
| 绯诲垪锛� | iCMOS® |
| ADC 鐨勬暩(sh霉)閲忥細 | 2 |
| 浣嶆暩(sh霉)锛� | 12 |
| 閲囨ǎ鐜囷紙姣忕锛夛細 | 1M |
| 鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� | 涓茶 |
| 杓稿叆鑼冨湇锛� | ±10 V |
| 鍦ㄤ互涓嬫浠朵笅鐨勯浕婧愶紙妯欐簴锛夛細 | 70mW @ 1MSPS |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 宸茬敤 IC / 闆朵欢锛� | AD7366 |
| 宸蹭緵鐗╁搧锛� | 鏉� |
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AD7366/AD7367
Rev. D | Page 9 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
DOUTA 1
2
3
ADDR
4
DGND
24
23
BUSY
22
CNVST
21
RANGE0
5
RANGE1
6
AGND
7
SCLK
20
CS
19
REFSEL
18
8
AGND
17
9
16
10
15
11
14
12
13
AD7366/
AD7367
TOP VIEW
(Not to Scale)
DOUTB
DCAPA
DCAPB
DVCC
AVCC
VSS
VA1
VA2
VB1
VB2
VDD
VDRIVE
06703-
002
Figure 2. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Description
1, 23
D
OUTA, DOUTB
Serial Data Outputs. The data output is supplied to each pin as a serial data stream. The bits are clocked out on
the falling edge of the SCLK input; 12 SCLK cycles are required to access a result from the AD7366, and 14 SCLK
cycles are required for the AD7367. The data simultaneously appears on both pins from the simultaneous con-
versions of both ADCs. The data stream consists of the 12 bits of conversion data for the AD7366 and 14 bits for
the AD7367 and is provided MSB first. If CS is held low for a further 14 SCLK cycles, on either DOUTA or DOUTB, the
data from the other ADC follows on that D
OUT pin. Note, the second serial result from the AD7366 is preceeded
by two zeros. Therfore data from a simultaneous conversion on both ADCs can be gathered in serial format on
either D
2
V
DRIVE
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface operates.
This pin should be decoupled to DGND. The voltage range on this pin is 2.7 V to 5.25 V and may be different
from the voltage at AV
CC and DVCC, but should never exceed either by more than 0.3 V. To achieve a throughput
rate of 1.12 MSPS for the AD7366 or 1 MSPS for the AD7367, V
DRIVE must be 鈮� 4.75 V.
3
DV
CC
Digital Supply Voltage, 4.75 V to 5.25 V. The DV
CC and AVCC voltages should ideally be at the same potential.
For best performance, it is recommended that the DV
CC and AVCC pins be shorted together, to ensure that the
voltage difference between them never exceeds 0.3 V even on a transient basis. This supply should be decoupled
to DGND. Place 10 F and 100 nF decoupling capacitors on the DV
CC pin.
4, 5
RANGE1,
RANGE0
Analog Input Range Selection, Logic Inputs. The polarity on these pins determines the input range of the analog
input channels. See the Analog Inputs section and Table 8 for details.
6
ADDR
Multiplexer Select, Logic Input. This input is used to select the pair of channels to be simultaneously converted,
either Channel 1 of both ADC A and ADC B, or Channel 2 of both ADC A and ADC B. The logic state on this pin is
latched on the rising edge of BUSY to set up the multiplexer for the next conversion.
7, 17
AGND
Analog Ground. Ground reference point for all analog circuitry on the AD7366/AD7367. All analog input signals
and any external reference signal should be referred to this AGND voltage. Both AGND pins should connect to
the AGND plane of a system. The AGND and DGND voltages should ideally be at the same potential and must
not be more than 0.3 V apart, even on a transient basis.
8
AV
CC
Analog Supply Voltage, 4.75 V to 5.25 V. This is the supply voltage for the ADC cores. The AV
CC and DVCC voltages
should ideally be at the same potential. For best performance, it is recommended that the DV
CC and AVCC pins be
shorted together, to ensure that the voltage difference between them never exceeds 0.3 V even on a transient
basis. This supply should be decoupled to AGND. Place 10 F and 100 nF decoupling capacitors on the AV
CC pin.
9, 16
D
CAPA, DCAPB
Decoupling Capacitor Pins. Decoupling capacitors are connected to these pins to decouple the reference buffer
for each respective ADC. For best performance, it is recommended that a 680 nF decoupling capacitor be used
on these pins. Provided the output is buffered, the on-chip reference can be taken from these pins and applied
externally to the rest of a system.
10
V
SS
Negative Power Supply Voltage. This is the negative supply voltage for the high voltage analog input structure
of the AD7366/AD7367. The supply must be less than a maximum voltage of 11.5 V for all analog input ranges.
See Table 7 for more details. Place 10 F and 100 nF decoupling capacitors on the V
SS pin.
11, 12
V
A1, VA2
Analog Inputs of ADC A. Both analog inputs are single-ended. The analog input range on these channels is
determined by the RANGE0 and RANGE1 pins.
13, 14
V
B2, VB1
Analog Inputs of ADC B. Both analog inputs are single-ended. The analog input range on these channels is
determined by the RANGE0 and RANGE1 pins.
15
V
DD
Positive Power Supply Voltage. This is the positive supply voltage for the high voltage analog input structure of
the AD7366/AD7367. The supply must be greater than a minimum voltage of 11.5 V for all analog input ranges.
See Table 7 for more details. Place 10 F and 100 nF decoupling capacitors on the V
DD pin.
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