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參數(shù)資料
| 型號： | EVAL-AD7328SDZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 27/37頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD7328 |
| 標準包裝： | 1 |
| 系列： | iCMOS® |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 1M |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 輸入范圍： | ±10 V |
| 在以下條件下的電源（標準）： | 31mW @ 1MSPS |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD7328 |
| 已供物品： | 板 |
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AD7328
Data Sheet
Rev. C | Page 32 of 36
MICROPROCESSOR INTERFACING
The serial interface on the AD7328 allows the part to be directly
connected to a range of different microprocessors. This section
explains how to interface the AD7328 with some common
microcontroller and DSP serial interface protocols.
The ADSP-21xx family of DSPs interfaces directly to the AD7328
the same supply voltage as that of the ADSP-21xx. This allows
the ADC to operate at a higher supply voltage than its serial inter-
face. The SPORT0 on the ADSP-21xx should be configured as
shown in Table 14.
Table 14. SPORT0 Control Register Setup
Setting
Description
TFSW = RFSW = 1
Alternative framing
INVRFS = INVTFS = 1
Active low frame signal
DTYPE = 00
Right justify data
SLEN = 1111
16-bit data-word
ISCLK = 1
Internal serial clock
TFSR = RFSR = 1
Frame every word
IRFS = 0
Internal receive frame sync
ITFS = 1
Internal transmit frame sync
The connection diagram is shown in Figure 54. The ADSP-21xx
has TFS0 and RFS0 tied together. TFS0 is set as an output, and
RFS0 is set as an input. The DSP operates in alternative framing
mode, and the SPORT0 control register is set up as described in
Table 14. The frame synchronization signal generated on TFS is
tied to CS and, as with all signal processing applications, requires
equidistant sampling. However, as in this example, the timer
interrupt is used to control the sampling rate of the ADC, and
under certain conditions equidistant sampling cannot be achieved.
AD73281
ADSP-21xx1
SCLK
SCLK0
CS
TFS0
RFS0
DOUT
DIN
DT0
DR0
VDD
VDRIVE
1ADDITIONAL PINS OMITTED FOR CLARITY.
04852-
037
Figure 54. Interfacing the AD7328 to the ADSP-21xx
The timer registers are loaded with a value that provides an
interrupt at the required sampling interval. When an interrupt
is received, a value is transmitted with TFS/DT (ADC control
word). The TFS is used to control the RFS and, hence, the reading
of data.
The frequency of the serial clock is set in the SCLKDIV register.
When the instruction to transmit with TFS is given (AX0 = TX0),
the state of the serial clock is checked. The DSP waits until the
SCLK has gone high, low, and high again before starting the trans-
mission. If the timer and SCLK are chosen so that the instruction
to transmit occurs on or near the rising edge of SCLK, data can
be transmitted immediately or at the next clock edge.
For example, if the ADSP-21xx has a master clock frequency of
16 MHz and the SCLKDIV register is loaded with the value 3,
an SCLK of 2 MHz is obtained, and eight master clock periods
elapse for every one SCLK period. If the timer registers are loaded
with the value 803, 100.5 SCLKs occur between interrupts and,
subsequently, between transmit instructions. This situation leads
to nonequidistant sampling because the transmit instruction occurs
on an SCLK edge. If the number of SCLKs between interrupts is
an integer of N, equidistant sampling is implemented by the DSP.
The ADSP-BF53x family of DSPs interfaces directly to the
AD7328 without requiring glue logic, as shown in Figure 55.
The SPORT0 Receive Configuration 1 register should be set up
as outlined in Table 15.
AD73281
ADSP-BF53x1
VDD
VDRIVE
SCLK
RSCLK0
DIN
DT0
DOUT
DR0
CS
RFS0
1ADDITIONAL PINS OMITTED FOR CLARITY.
04852-
038
Figure 55. Interfacing the AD7328 to the ADSP-BF53x
Table 15. SPORT0 Receive Configuration 1 Register
Setting
Description
RCKFE = 1
Sample data with falling edge of RSCLK
LRFS = 1
Active low frame signal
RFSR = 1
Frame every word
IRFS = 1
Internal RFS used
RLSBIT = 0
Receive MSB first
RDTYPE = 00
Zero fill
IRCLK = 1
Internal receive clock
RSPEN = 1
Receive enable
SLEN = 1111
16-bit data-word
TFSR = RFSR = 1
Transmit and receive frame sync
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