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| 型號： | EVAL-AD7194EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 44/57頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVAL BOARD FOR AD7194 |
| 設(shè)計資源： | EVAL-AD7zzzEBZ Schematic AD7194 Gerber Files |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 24 |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 工作溫度： | -40°C ~ 105°C |
| 已用 IC / 零件： | AD7194 |
| 已供物品： | 板，線纜 |
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AD7194
Data Sheet
Rev. A | Page 48 of 56
FAST SETTLING MODE (SINC3 FILTER)
In fast settling mode, the settling time is close to the inverse of
the first filter notch. Therefore, the user can achieve 50 Hz and/or
60 Hz rejection at an output data rate close to 1/50 Hz or 1/60 Hz.
The settling time is equal to 1/output data rate. Therefore, the
conversion time is constant when converting on a single channel
or when converting on several channels. There is no added
latency when switching channels.
The fast settling mode is enabled using Bit AVG1 and Bit AVG0
in the mode register. A postfilter is included after the sinc4 filter.
The postfilter averages by 2, 8, or 16, depending on the settings
of the AVG1 and AVG0 bits.
SINC3/SINC4
POST FILTER
MODULATOR
ADC
CHOP
08566-
059
Figure 60. Fast Settling Mode, Sinc3 Filter
Output Data Rate and Settling Time, Sinc3 Filter
With chop disabled, the output data rate is
fADC = fCLK/((3 + Avg – 1)× 1024 × FS[9:0])
fADC is the output data rate.
fCLK is master clock (4.92 MHz nominal).
Avg is the average.
FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the
mode register.
If AVG1 = AVG0 = 0, the fast settling mode is not enabled. In
this case, the preceding equation is not relevant.
The settling time is equal to
tSETTLE = 1/fADC
Table 35 lists some sample FS words and the corresponding
output data rates and settling times.
Table 35. Examples of Output Data Rates and the
Corresponding Settling Time (Fast Settling Mode, Sinc3)
FS[9:0]
Average
Output Data
Rate (Hz)
Settling
Time (ms)
96
16
2.78 Hz
360 ms
30
16
8.9 Hz
112.5 ms
6
16
44.44 Hz
22.5 ms
5
16
53.3 Hz
18.75 ms
If the analog input channel is changed, there is no additional
delay in generating valid conversions and the device functions
as a zero latency ADC.
CHANNEL
CONVERSIONS
CHANNEL A
CH A
CH B
CHANNEL B
1/
fADC
CH B
08566-
060
Figure 61. Fast Settling, Sinc3 Filter
When the device is converting on a single channel and a step
change occurs on the analog input, the ADC does not detect
the change and continues to output conversions. When the step
change is synchronized with the conversion, only fully settled
results are output from the ADC. However, if the step change is
asynchronous to the conversion process, one intermediate result
is not completely settled (see Figure 62).
ANALOG
INPUT
ADC
OUTPUT
VALID
1/
fADC
08566-
061
Figure 62. Step Change on Analog Input, Sinc3 Filter
50 Hz/60 Hz Rejection, Sinc3 Filter
Figure 63 shows the frequency response when FS[9:0] is set to 6
and the postfilter averages by 16. This gives an output data rate
of 44.44 Hz when the master clock is 4.92 MHz. The sinc filter
places the first notch at
fNOTCH = fCLK/(1024 × FS[9:0])
The postfiltering places notches at fNOTCH/Avg (Avg is the
amount of averaging) and multiples of this frequency. There-
fore, when FS[9:0] is set to 6 and the postfilter averaging is 16,
a notch is placed at 800 Hz due to the sinc filter and notches are
placed at 50 Hz and multiples of 50 Hz due to the postfilter.
The notch at 50 Hz is a first-order notch. Therefore, the notch is
not wide. This means that the rejection at 50 Hz exactly is good,
assuming a stable 4.92 MHz master clock. However, in a band of
50 Hz ± 1 Hz, the rejection degrades significantly. The rejection at
50 Hz ± 0.5 Hz is 40 dB minimum, assuming a stable clock; there-
fore, a good master clock source is recommended when using fast
settling mode.
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