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參數(shù)資料
| 型號(hào)： | EVAL-AD7194EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 16/57頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVAL BOARD FOR AD7194 |
| 設(shè)計(jì)資源： | EVAL-AD7zzzEBZ Schematic AD7194 Gerber Files |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 24 |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 工作溫度： | -40°C ~ 105°C |
| 已用 IC / 零件： | AD7194 |
| 已供物品： | 板，線纜 |
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AD7194
Data Sheet
Rev. A | Page 22 of 56
Bit Location
Bit Name
Description
MR12
CLK_DIV
Clock divide-by-2. When CLK_DIV is set, the master clock is divided by 2. For normal conversions, set this
bit to 0. When performing internal full-scale calibrations, this bit must be set when AVDD is less than
4.75 V. The calibration accuracy is optimized when chop is enabled and a low output data rate is used
while performing the calibration. When AVDD is greater than or equal to 4.75 V, it is not compulsory to set
the CLK_DIV bit when performing internal full-scale calibrations.
MR11
Single
Single cycle conversion enable bit. When this bit is set, the AD7194 settles in one conversion cycle so
that it functions as a zero latency ADC. This bit has no effect when multiple analog input channels are
enabled or when the single conversion mode is selected. If the fast-settling filter is enabled, this bit
(single) does not have an effect on the conversions unless chopping is also enabled.
MR10
REJ60
This bit enables a notch at 60 Hz when the first notch of the sinc filter is at 50 Hz. When REJ60 is set, a
filter notch is placed at 60 Hz when the sinc filter first notch is at 50 Hz. This allows simultaneous 50 Hz/
60 Hz rejection.
MR9 to MR0
FS9 to FS0
Filter output data rate select bits. The 10 bits of data programmed into these bits determine the filter
cutoff frequency, the position of the first notch of the filter, and the output data rate for the part. In
association with the gain selection, they also determine the output noise and, therefore, the effective
resolution of the device (see Table 6 through Table 11).
When chop is disabled, fast settling mode is disabled and continuous conversion mode is selected
Output Data Rate = (MCLK/1024)/FS
where FS is the decimal equivalent of the code in Bit FS0 to Bit FS9 within the range of 1 to 1023, and
MCLK is the master clock frequency.
With a nominal MCLK of 4.92 MHz, this results in an output data rate from 4.69 Hz to 4.8 kHz. With chop
disabled and fast settling mode disabled, the first notch frequency is equal to the output data rate when
converting on a single channel.
When chop is enabled (fast settling mode disabled)
Output Data Rate = (MCLK/1024)/(N × FS)
where FS is the decimal equivalent of the code in Bit FS0 to Bit FS9 within the range of 1 to 1023, and
MCLK is the master clock frequency.
With a nominal MCLK of 4.92 MHz, this results in a conversion rate from 4.69/N Hz to 4.8/N kHz, where N
is the order of the sinc filter. The first notch frequency of the sinc filter is equal to
N × Output Data Rate
The chopping introduces notches at odd integer multiples of
Output Data Rate/2
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