參數(shù)資料
型號(hào)： ES25P80
廠商： 優(yōu)先(蘇州)半導(dǎo)體有限公司
英文描述： 8Mbit CMOS 3.0 Volt Flash Memory with 75Mhz SPI Bus Interface
中文描述： 8Mbit的CMOS 3.0伏的閃存與75MHz的SPI總線接口
文件頁數(shù)： 7/35頁
文件大小： 450K
代理商： ES25P80
ESI
7
Rev. 0D May, 11, 2006
ES25P80
Excel Semiconductor inc.
ADVANCED INFORMATION
Protection Modes
The SPI memory device boasts the following data
protection mechanisms
1) All instructions that modify data must be preceded
by a Write Enable(WREN) instruction to set the
Write Enable Latch (WEL) bit. This bit is returned to
its reset state by the following events :
- Power-up
- WRDI instruction completion
- WRSR instruction completion
- PP instruction completion
- SE instruction completion
- BE instruction completion
2) The Block Protect (BP2, BP1, BP0) bits allow part
of the memory to be configured as read-only. This is
the Software Protected Mode (SPM).
3) The Write Protect (W#) signal works in coopera-
tion with the Status Register Write Disable (SRWD)
bit to enable write-protection. This is the Hardware
Protected Mode (HPM).
4) Program, Erase and Write Status Register instruc-
tions are checked to verify that they consist of a
number of clock pulses that is a multiple of eight,
before they are accepted for execution.
If the falling edge does not coincide with Serial Clock
(SCK) being Low, the Hold condition starts after
Serial Clock (SCK) next goes Low. Similarly, If the
rising edge does not coincide with Serial Clock
(SCK) being Low, the Hold condition ends after
Serial Clock (SCK) next goes Low (Figure 3).
During the Hold condition, the Serial Data Output
(SO) is high impedance, and Serial Data Input (SI)
and Serial Clock (SCK) are Don’t Care.
Normally, the device remains selected, with Chip
Select (CS#) driven Low, for the entire duration of
the Hold condition. This ensures that the state of the
internal logic remains unchanged from the moment
of entering the Hold condition.
If Chip Select (CS#) goes High while the device is in
the Hold condition, this has the effect of resetting the
internal logic of the device. To restart communication
with the device, it is necessary to drive Hold
(HOLD#) High, and then to drive Chip Select (CS#)
Low. This prevents the device from going back to the
Hold condition.
Table 1. Protected Area Sizes
Protected Memory
Area (Top Level)
Status Register Content
Memory Content
BP2 Bit
BP1 Bit
BP0 Bit
Protected Area
Unprotected Area
0
0
0
0
none
00000 ~ FFFFF
1 / 16
0
0
1
F0000 ~ FFFFF
00000 ~ EFFFF
1 / 8
0
1
0
E0000 ~ FFFFF
00000 ~ DFFFF
1 / 4
0
1
1
C0000 ~ FFFFF
00000 ~ BFFFF
1 / 2
1
0
0
80000 ~ FFFFF
00000 ~ 7FFFF
All
1
0
1
00000 ~ FFFFF
+ parameter page
none
All
1
1
0
00000 ~ FFFFF
+ parameter page
none
All
1
1
1
00000 ~ FFFFF
+ parameter page
none
相關(guān)PDF資料
PDF描述
ES25P80-75CC2R 8Mbit CMOS 3.0 Volt Flash Memory with 75Mhz SPI Bus Interface
ES25P80-75CC2T 8Mbit CMOS 3.0 Volt Flash Memory with 75Mhz SPI Bus Interface
ES25P80-75CC2Y 8Mbit CMOS 3.0 Volt Flash Memory with 75Mhz SPI Bus Interface
ES25P80-75CG2R 8Mbit CMOS 3.0 Volt Flash Memory with 75Mhz SPI Bus Interface
ES25P80-75CG2T 8Mbit CMOS 3.0 Volt Flash Memory with 75Mhz SPI Bus Interface
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ES25P80-75CC2R 制造商:EXCELSEMI 制造商全稱:EXCELSEMI 功能描述:8Mbit CMOS 3.0 Volt Flash Memory with 75Mhz SPI Bus Interface
ES25P80-75CC2T 制造商:EXCELSEMI 制造商全稱:EXCELSEMI 功能描述:8Mbit CMOS 3.0 Volt Flash Memory with 75Mhz SPI Bus Interface
ES25P80-75CC2Y 制造商:EXCELSEMI 制造商全稱:EXCELSEMI 功能描述:8Mbit CMOS 3.0 Volt Flash Memory with 75Mhz SPI Bus Interface
ES25P80-75CG2R 制造商:EXCELSEMI 制造商全稱:EXCELSEMI 功能描述:8Mbit CMOS 3.0 Volt Flash Memory with 75Mhz SPI Bus Interface
ES25P80-75CG2T 制造商:EXCELSEMI 制造商全稱:EXCELSEMI 功能描述:8Mbit CMOS 3.0 Volt Flash Memory with 75Mhz SPI Bus Interface
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