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參數(shù)資料
| 型號： | ES25P80 |
| 廠商： | 優(yōu)先(蘇州)半導(dǎo)體有限公司 |
| 英文描述： | 8Mbit CMOS 3.0 Volt Flash Memory with 75Mhz SPI Bus Interface |
| 中文描述： | 8Mbit的CMOS 3.0伏的閃存與75MHz的SPI總線接口 |
| 文件頁數(shù)： | 18/35頁 |
| 文件大?。?/td> | 450K |
| 代理商： | ES25P80 |
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ESI
18
Rev. 0D May, 11, 2006
ES25P80
Excel Semiconductor inc.
ADVANCED INFORMATION
Page Program (PP)
The Page Program (PP) instruction allows bytes to
be programmed in the memory (changing from 1 to
0). Before it can be accepted, a Write Enable
(WREN) instruction must previously have been exe-
cuted. After the Write Enable (WREN) instruction
has been decoded, the device sets the Write Enable
Latch (WEL).
The Page Program (PP) instruction is entered by
driving Chip Select (CS#) Low, followed by the
instruction code, three address bytes and at least
one data byte on Serial Data Input (SI). Chip Select
(CS#) must be driven Low for the entire duration of
the sequence.
The instruction sequence is shown in Figure 13.
If more that 256 data bytes are sent to the device,
the addressing will wrap to the beginning of the
same page, previously latched data are discarded
and the last 256 data bytes are guaranteed to be
programmed correctly within the same page.
If fewer than 256 data bytes are sent to device, they
are correctly programmed at the requested
addresses without having any effects on the other
bytes of the same page.
Chip Select (CS#) must be driven High after the
eighth bit of the last data byte has been latched in,
otherwise the Page Program (PP) instruction is not
executed. As soon as Chip Select (CS#) is driven
High, the self-timed Page Program cycle (whose
duration is t
PP
) is initiated. While the Page Program
cycle is in progress, the Status Register may be
read to check the value of the Write In Progress
(WIP) bit. The Write In Progress (WIP) bit is 1 dur-
ing the self-timed Page Program cycle, and is 0
when it is completed. At some unspecified time
before the cycle is completed, the Write Enable
Latch (WEL) bit is reset.
A Page Program (PP) instruction applied to a page
that is protected by the Block Protect (BP2, BP1,
BP0) bits (see Table 1) is not executed.
0
0 0
0
0
0 1 0
0
1 2
3
4
5
6 7
8
9 10
28 29 30
31 32 33
34 35
36 37 38 39
SCK
CS#
SI
MSB
23
Instruction
24-Bit Address
Figure 13. Page Program (PP) Instruction Sequence
Data Byte1
MSB
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
SCK
CS#
SI
MSB
Data Byte 2
MSB
Data Byte 3
Data Byte256
MSB
2
2
2
2
2
2
2
2
22 21
2
1
0
2
1
0
5
4
3
7
6
2
1
0
5
4
3
7
6
2
1
0
5
4
3
7
6
2
1
0
5
4
3
7
6
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ES25P80-75CC2R | 8Mbit CMOS 3.0 Volt Flash Memory with 75Mhz SPI Bus Interface |
| ES25P80-75CC2T | 8Mbit CMOS 3.0 Volt Flash Memory with 75Mhz SPI Bus Interface |
| ES25P80-75CC2Y | 8Mbit CMOS 3.0 Volt Flash Memory with 75Mhz SPI Bus Interface |
| ES25P80-75CG2R | 8Mbit CMOS 3.0 Volt Flash Memory with 75Mhz SPI Bus Interface |
| ES25P80-75CG2T | 8Mbit CMOS 3.0 Volt Flash Memory with 75Mhz SPI Bus Interface |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ES25P80-75CC2R | 制造商:EXCELSEMI 制造商全稱:EXCELSEMI 功能描述:8Mbit CMOS 3.0 Volt Flash Memory with 75Mhz SPI Bus Interface |
| ES25P80-75CC2T | 制造商:EXCELSEMI 制造商全稱:EXCELSEMI 功能描述:8Mbit CMOS 3.0 Volt Flash Memory with 75Mhz SPI Bus Interface |
| ES25P80-75CC2Y | 制造商:EXCELSEMI 制造商全稱:EXCELSEMI 功能描述:8Mbit CMOS 3.0 Volt Flash Memory with 75Mhz SPI Bus Interface |
| ES25P80-75CG2R | 制造商:EXCELSEMI 制造商全稱:EXCELSEMI 功能描述:8Mbit CMOS 3.0 Volt Flash Memory with 75Mhz SPI Bus Interface |
| ES25P80-75CG2T | 制造商:EXCELSEMI 制造商全稱:EXCELSEMI 功能描述:8Mbit CMOS 3.0 Volt Flash Memory with 75Mhz SPI Bus Interface |
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