參數(shù)資料
型號(hào)： ES25P80-75IG2R
廠商： 優(yōu)先(蘇州)半導(dǎo)體有限公司
英文描述： 8Mbit CMOS 3.0 Volt Flash Memory with 75Mhz SPI Bus Interface
中文描述： 8Mbit的CMOS 3.0伏的閃存與75MHz的SPI總線接口
文件頁(yè)數(shù)： 11/35頁(yè)
文件大?。?/td> 450K
代理商： ES25P80-75IG2R
ESI
11
Rev. 0D May, 11, 2006
ES25P80
Excel Semiconductor inc.
ADVANCED INFORMATION
0 0 0 0 0 1 0 0
0 0 0 0 0 1 1 0
Write Enable (WREN)
The Write Enable (WREN) instruction (Figure 4) sets
the Write Enable Latch (WEL) bit. The Write Enable
Latch (WEL) bit must be set prior to every Page Pro-
gram (PP or PPP), Erase (SE, BE or PE) and Write
Status Register (WRSR) instruction. The Write
Enable (WREN) instruction is entered by driving
Chip Select (CS#) Low, sending the instruction code,
and then driving Chip Select (CS#) High.
Write Disable (WRDI)
The Write Disable (WRDI) instruction (Figure 5)
resets the Write Enable Latch (WEL) bit. The Write
Disable (WRDI) instruction is entered by driving Chip
Select (CS#) Low, sending the instruction code, and
then driving Chip Select (CS#) High.
The Write Enable (WEL) bit is reset under the follow-
ing conditions :
- Power-up
- WRDI instruction completion
- WRSR instruction completion
- PP instruction completion
- SE instruction completion
- BE instruction completion
0 1 2 3 4 5 6 7
Figure 4. Write Enable ( WREN ) Instruction Sequence
SCK
CS#
SI
SO
Instruction
High Impedance
0
1 2 3 4 5 6 7
Figure 5. Write Disable ( WRDI ) Instruction Sequence
SCK
CS#
SI
SO
Instruction
High Impedance
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ES25P80-75IG2T 制造商:EXCELSEMI 制造商全稱:EXCELSEMI 功能描述:8Mbit CMOS 3.0 Volt Flash Memory with 75Mhz SPI Bus Interface
ES25P80-75IG2Y 制造商:EXCELSEMI 制造商全稱:EXCELSEMI 功能描述:8Mbit CMOS 3.0 Volt Flash Memory with 75Mhz SPI Bus Interface
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