參數(shù)資料
型號： EPM7128ABC100-6
廠商： ALTERA CORP
元件分類： PLD
英文描述： EE PLD, 6 ns, PBGA100
文件頁數(shù)： 50/51頁
文件大小： 1559K
代理商： EPM7128ABC100-6
602
Altera Corporation
MAX 7000A Programmable Logic Device Family Data Sheet
Preliminary Information
The MAX+PLUS II development system automatically optimizes
product-term allocation according to the logic requirements of the design.
For registered functions, each macrocell flipflop can be individually
programmed to implement D, T, JK, or SR operation with programmable
clock control. The flipflop can be bypassed for combinatorial operation.
During design entry, the designer specifies the desired flipflop type; the
MAX+PLUS II software then selects the most efficient flipflop operation
for each registered function to optimize resource utilization.
Each programmable register can be clocked in three different modes:
s
Global clock signal. This mode achieves the fastest clock-to-output
performance.
s
Global clock signal enabled by an active-high clock enable. A clock
enable is generated by a product term. This mode provides an enable
on each flipflop while still achieving the fast clock-to-output
performance of the global clock.
s
Array clock implemented with a product term. In this mode, the
flipflop can be clocked by signals from buried macrocells or I/O pins.
Two global clock signals are available in MAX 7000A devices. As shown
in Figure 1, these global clock signals can be the true or the complement
of either of the global clock pins, GCLK1 or GCLK2.
Each register also supports asynchronous preset and clear functions. As
shown in Figure 2, the product-term select matrix allocates product terms
to control these operations. Although the product-term-driven preset and
clear from the register are active high, active-low control can be obtained
by inverting the signal within the logic array. In addition, each register
clear function can be individually driven by the active-low dedicated
global clear pin (GCLRn). Upon power-up, each register in a MAX 7000AE
device may be set to either a high or low state. This power-up state is
specified at design entry.
All MAX 7000A I/O pins have a fast input path to a macrocell register.
This dedicated path allows a signal to bypass the PIA and combinatorial
logic and be clocked to an input D flipflop with an extremely fast (as low
as 2.5 ns) input setup time.
相關(guān)PDF資料
PDF描述
EPM7128ABC100-7 EE PLD, 7.5 ns, PBGA100
EPM7128ABI100-10 EE PLD, 10 ns, PBGA100
EPM7128ABI100-12 EE PLD, 12 ns, PBGA100
EPM7128ABI100-6 EE PLD, 6 ns, PBGA100
EPM7128ABI100-7 EE PLD, 7.5 ns, PBGA100
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EPM7128AE 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Programmable Logic Device
EPM7128AEFC100-10 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX 7000 128 Macro 84 IOs RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
EPM7128AEFC100-10N 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX 7000 128 Macro 84 IOs RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
EPM7128AEFC100-5 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX 7000 128 Macro 84 IOs RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
EPM7128AEFC100-5N 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX 7000 128 Macro 84 IOs RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
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